Trends:Design for Manufacture (DFM) Trends

Design for Manufacture (DFM) Trends

With each reduction in IC feature size, additional manufacturing issues arise. These include increased complexity, higher clock frequencies, power dissipation, component density, and reliability.

The effects of the manufacturing process on the design need to be understood. Chip designers, lithography, mask-making, processing, and test engineers need better two-way communication.

More manufacturing-aware tools are coming onto the market. These tools take into account manufacturing tolerances, voltage sensitivity, and technology constraints. Considering manufacturing early in the design process can significantly improve the eventual semiconductor chip yield.

Significant DFM trends include:

  • Design Redundancy

  • Chip-to-Chip Differences

  • Mask Enhancements

Design Redundancy

One trend is greater use of redundancy to achieve a higher manufacturing yield. This approach has been most successful with memories and FPGAs. Memory blocks incorporate spare memory cells used for self-repair of hard failures. Redundancy also enables repair of soft errors (errors due to noise or manufacturing tolerance variations). Now similar techniques are being applied to the logic circuits.

Chip-to-Chip Differences

Another trend is to include the manufacturing process variations in design analysis. Chips can differ from one another, even when made on the same wafer. (As in baking a batch of cookies, each cookie is unique.)

The analysis uses defect density information (the predicted number of defects at each manufacture step). It identifies probable failure due to the normal manufacturing variations. The analysis applies within the chip, and from chip to chip across the wafer.

One example is clock distribution which must span a large chip area. Manufacturing variations can cause clocks to arrive at the wrong times. The designer uses circuit design and layout analysis to reduce the effect of expected manufacturing variations.

Mask Enhancements

Will this incredible shrinking ever end? The end has been predicted repeatedly, but so far it hasn't happened. The original National Technology Roadmap for Semiconductors predicted 70 nm (0.07 micron) feature size by 2010. A 50-nm process was announced as early as 2002. (However, people are encountering many new problems at 90 nm and below. New transistor models and tools are required to account for these new issues.)

Whereas mask costs used to be relatively low (about $3,000), mask sets (all the layers) now run over $1,000,000. A SEMATECH survey showed that as few as only six wafers were run for some ASIC parts. At that rate, the chips must be priced at several hundred dollars just to break even. Some industry observers predict the end of ASICs due to this low volume and high mask cost. (Of course, the FPGA marketing folks have been predicting the end of ASICs for years...)

There is still life in the optical lithography used to make the manufacturing masks. Various optical tricks (Resolution Enhancement Techniques) are used to improve the resolution and mask image. Two main approaches are Phase Shifting Mask (PSM) and Optical Proximity Correction (OPC).

These techniques require EDA programs to prepare the chip design data files for the mask shop. Currently, the tightest specifications apply to everything on the mask, whether critical or not. There is no range or scale for defects.

The IC designers must learn and adjust for the mask maker's constraints. Alternatively, the IC designer's intent must be passed down to maskmaking and manufacturing. This would allow variable specifications on the masks to be implemented. It is not clear which approach will be taken.

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