The Business of EDA:The Time-to-Market Competition

The Time-to-Market Competition

Frank:

In full custom design, all the IC parts are optimized to give the fastest and densest layout. Early ICs were all small custom-designed parts. They were sold as standard building blocks to multiple buyers. The buyers would use them to build many different kinds of products.

Since timetomarket is so important to ICs, companies invented semi-custom architecture to speed up chip design. The IC architecture is how the transistors are structured (or arranged) on the chip. The idea is to make most of the chip standard, with some tailoring (customizing) done for each customer application.

An analogy is furniture with a common design, but a wide choice of cover material. Another analogy is a new car with a standard basic design but with many colors and options. If you buy what they offer on the lot, you can get it quickly.

There are three main kinds of semi-custom architecture: gate array (GA), standard cell (SC), and field programmable gate arrays (FPGAs). Each requires some specialized EDA tools. Either the manufacturer or the customer customizes each kind.

The GAs and SCs are called Application Specific Integrated Circuits (ASICs). (FPGAs are not ASICs per se, but compete directly with them.) Each ASIC is customized for a specific customer.

Gate Arrays: The IC is covered with an array (fixed rows and columns) of identical logic gate circuits defined by the manufacturer. (Think of rows of identical cars in a rectangular parking lot.) The customer defines how the gates should be wired together. It is the wiring, implemented by the manufacturer, which customizes the gate array.

Standard Cells: The customer chooses logic cells (groups of gates) from a library of standardized cells. A cell can be much larger and more complex than a simple gate. (Think of trucks in the parking lot instead of cars and choosing the type of truck for each parking spot location.) The customer defines how they should be wired together. Thus both the choice of cells and the wiring are custom. The manufacturer implements the cells in the chosen locations on the chip and does the wiring.

Field Programmable Gate Arrays (FPGAs): These are fixed arrays of complex gates defined by the manufacturer. The interconnect wiring of these gates is a fixed multilevel matrix or mesh of wire segments defined by the manufacturer. The customer defines the function of each group of gates or logic cells, and how they should be wired together.

Each possible connection point is a selectable fusible link or a switch controlled by a memory cell embedded in the chip. The customer defines how they should be wired together. EDA software then chooses the right combination of wire segments and connects them up by selecting the needed link or switch points.

The same FPGA chip is mass-produced for many customers. Each customer then does the custom wiring in seconds at their own facility or in the field. This makes for very a fast TTM.

The fusible link programmable chips are usually programmable just one time. The memory-based switch type chips can be reprogrammed for easy design modification. Most FPGA memory-based chips lose their memory when power is off (volatile), but some use flash memory to be non-volatile.

However, for the same function, FPGAs may take 10-20X more chip area than SC ASICs. Therefore, they are more expensive and slower for the same amount of circuitry. Vendors make many variants of each architecture.

As I mentioned, each of these architectures uses different EDA tools, particularly for the physical layout design. The FPGA vendors usually supply their own tools, free. Each company's tools are optimized for its architecture. Only a few FPGA tools are from pure EDA companies.

Nora:

How do the engineers decide which approach to use?

Frank:

Customers choose an architecture depending on their IC complexity, TTM, cost, and volume needs. The cost/volume crossover point depends on the application, of course. But a recent rule-of-thumb had FPGAs as more cost-effective up to about 1,000 units.

If a change is required, the ASICs need to rework (re-spin) the silicon, whereas the FPGAs do not. SCs may require all the mask layers to be redone, and GAs require only the top metal interconnection layer (partial re-spin).

Each approach has its merits and the competition is fierce. Heated debates occur on conference panels about which is the better approach. This competition is part of the business landscape for EDA tools.

Let me sketch you a quick table for comparison. (See Table 2.1.)

Note that for low-volume and low-speed applications, the FPGA's low cost and short TTM win. FPGAs also fit applications which are likely to change frequently. Military and aerospace firms are major FPGA users. There are also EDA tools to convert an FPGA to an ASIC, should the demand and number of units needed increase.

Note that the SC usually wins for high volume, stable, medium performance applications. (GA use has steadily declined.)

Custom chips are still used for very high-volume, high-performance, or very low-power applications.

Nora:

The IC variations are more complicated than I realized.

Frank:

Well, IC types develop over time. I mention ASICs because most ICs are usually one type of ASIC or another.

There are also combinations with FPGA blocks on an SC chip. Some chips have SC blocks embedded in an FPGA. This can be a problem since some design steps and EDA tools differ for each architecture. And other chip architectures embed increasing numbers of memory blocks into ASICs and FPGAs.