Design using Standard Description Languages:Operators

Operators

VHDL offers a large set of different operators for defining comparisons, boolean equations, or arithmetic in RTL models. Operators are always connected with objects (signals, variables or arrays) of a specific type (BIT, BOOLEAN, INTEGER). At the definition of a type it is necessary to supply a set of operators. Looking at the predefined types BIT and BOOLEAN, as well as their arrays, this is carried out automatically. If there are no implicit operators, either one’s own operators must be added or the behavior of built in operators must be modified. The simple enumerator STD_LOGIC is the most popular type for which a package in the IEEE library implements operators. As a rule, a test to ‘equal’ or ‘not equal’ values is implemented for all types, because a test bit by bit is sufficient to perform that test.

Quite on the contrary, there is a difference in performing an addition with, e.g., integer objects or enumerators. The enumerators need specific instructions in order to provide a right result. An overview of available operators is shown in table 4.18. Some predefined operators for the different types are shown by table 4.19.

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Standard Operators

The standard separates operators into individual classes. Different priorities (fig. 4.20) define the sequence of execution, especially when there are several operators in one expression. E.g., the result of the example is 14, not 20, because multiplication has a higher priority than addition. If an expression has several operators of the same priority, processing is performed according to the arrangement in the expression from left to the right: 2 − 3 + 4 will be interpreted as (2 − 3) + 4.

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The following logical operations are available: NOT, AND, NAND, OR, NOR, XOR, and XNOR.

A boolean combination returns TRUE or FALSE. Opposite to other programming languages, in VHDL all logical operators except the NOT operator have the same priority. The use of brackets is necessary under all circumstances when having mixed types of operators:

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Logical operators can be handled easily by a synthesis tool which uses a circuit model using boolean equations.

It is possible to find the VHDL operators in the internal description which has sum or product terms. However, the result is influenced by many factors. Depending on constraints, a re-structuring of the circuit occurs during synthesis. For example, optimizing area or speed decides about the use of operators. The same goes for the choice of a target technology. Having no XOR gate available would cause a transformation to sum (OR) and product terms(AND) such as

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Relational Operators

A most frequent use of relational operators is the test of numerical types (see table 4.22). Such a test has the format, e.g., (a < b) or (a > 123). Since the result is of the type BOOLEAN (which is TRUE to provide a newly introduced type with a set of suitable operators. Certainly the most needed operators are comparing operators (table 4.22) and arithmetic operators.

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