Graphical Specification of System Behavior

Introduction

Since the beginning of the 80’s schematic entry of digital circuits has been replaced by hardware description languages. This was driven by the spreading use of synthesis tools which needed a language for design entry. To avoid a variety of en- try languages the hardware description languages VHDL and Verilog were standardized. The algorithms which can be coded using these languages had been presented graphically in the design of electronic circuits long before.

Clear Style of Representation

The graphical description of algorithms and behavior has the advantage that these algorithms can be presented in a way more transparent than code. The graphical display of sequences can be understood by humans more easily, whereas the coded display of sequences is more suitable for a computer. Although VHDL is a hardware description language it is becoming more and more difficult to obtain a general view when complexity increases. The following VHDL code and the

 

The Design Cycle using a Graphical Specification

In principle the design cycle of a circuit presented in fig. 4.5 of chapter 4 is the same one. The only difference to fig. 5.2 is that the specification phase and the design phase can be done using a textual description (e.g., VHDL) or prior to that by a graphical description. Derived from the graphical description, a textual description (e.g., VHDL or Verilog) is generated automatically. It must be noted that the graphical description of the behavior is nothing more than the schematic representation of a VHDL or Verilog description. Therefore as a rule VHDL or Verilog syntax must be used when producing graphical input. Without knowing the hardware description language it is not possible to develop a circuit using graphical entry tools only

Ways of Graphical Descriptions

The structuring of a design can be done by using block diagrams. The functional description of parts of the design can be given in a graphical manner using truth tables, flow charts, or state transition diagrams.

Block Diagrams

Normally block diagrams structure a design ac- cording to its functional units. In a complex design block diagrams define the structure of the circuit. Blocks are connected by signals. Block diagrams can show a hierarchy; each block can consist of several additional blocks (see fig. 5.3). If a block does not contain any other blocks the lowest level of hierarchy is reached. Therefore a functional description must be assigned to that block. This functional description can be a truth table, a flow chart, a state transition table, or HDL text.

Truth Tables

Truth tables (see the example of fig. 5.4), often called function tables, are used to describe combi- natorial circuits. Thus decoders and multiplexers can be described clearly.

In a flow chart the following elements are typically used:

• assignment elements;

• decision elements;

• wait elements;

• loop elements.

All elements are connected with each other by ar- rows. Although flow charts can describe all kinds of functions, their prime use is to generate the so called test benches for testing a circuit during the specification phase and the design phase.

Similarly to block diagrams, the number of ele- ments per sheet should be kept small in order to

make the presentation readable. Therefore in large designs it makes sense to structure the flow charts hierarchically. The flow chart of the counter in fig. 5.1 is shown in fig. 5.6 using a hierarchical structure.

The automatically generated VHDL code of the counter is identical to that produced by the one derived from the flow chart fig. 5.1.

State Diagrams

State diagrams are a way of displaying a state machine graphically. In this case a state machine is used to model a sequential circuit. The sequential

circuit is characterized by a finite number of states and state-transitions.

The state machine; being a well known and struc- tured method of describing systems; allows one to describe many problems.

Principles of Sequential Circuits

There are two kinds of state machines used which can be combined:

• Mealy state machine; and

• Moore state machine.

These two kinds vary only in the way in which output signals are produced. Because of that it can be said that an output signal has a ‘Moore’ or a ‘Mealy’ behavior.

Differences of sequential circuits should be pointed out in brief, in order to explain the graphical representation shown in a flow chart.

State diagram of the Mealy state machine

Output signals produced by a Mealy state ma- chine depend on its internal state and on its input signals.

Thus having a sequential circuit of Mealy type, output signals can change state, when an input signal changes state. This change of the output signal is independent of a change of the clock. Certainly if a clock event takes place the output signals can change too (see fig. 5.7).

Priorities of State Transitions

To avoid ambiguity when leaving a state, state transitions have priorities assigned. This allows a simplified notation of the condition causing a transition of state. These priority assignments are converted to IF... THEN... ELSE threads in VHDL code (see fig. 5.12).

The numbers attached to the state transitions identify the priority, whereas the smallest number is equivalent to the highest priority

Transitions without a condition

When there are multiple conditional transitions to leave a state and that one transition is to be made in any case, it is possible to add an unconditional transition (see state s2 in fig. 5.13).

The state transition from s2 to s0 will always be performed, because the transition with a priority 3 is an unconditional transition. Of course, it is also possible to add a state transition without condition and assignment. This state transition causes only

Factorization of State Transitions

An additional way of increasing transparency of the graphical description and of reducing the number of conditions is to factorize the transitions. Here state transfers depending on several conditions can be split if some conditions are the same

Interrupt

An interrupt represents an element which makes it possible to leave all states when a particular con- dition is met. Therefore the entry of lots of state transitions; otherwise necessary; can be omitted (fig. 5.15).

Hierarchy

Just the same as when drawing a flow chart, it is reasonable in a description of a state diagram not to put too many elements on one page. Because of that a hierarchy can be built up, in state diagrams

Here the hierarchy is established by a state, that has been declared to be hierarchical, which holds additional states. It depends on the skill of the designer, to combine states in a reasonable way and to increase readability by that (fig. 5.16, 5.17 and 5.18).

Concurrent State Diagrams

If the behavior of a circuit can be described by not connected state diagrams, most of the graphical

Waiting

Patternsend

tools offer a possibility of realizing several state diagrams in one single block. These state diagrams share the same interfaces, the same local declarations, and the same references.

Setting of special properties to generate the HDL code

As shown in chapter 4, high level languages need signal declarations and conventions in order to code the states, as well as statements describing how to drive the clock and reset signals. Also the generator tool must have information dealing with the HDL style, such as for example the use of CASE or IF statements. As the number of possibilities is final, all these choices can be made in corresponding pop up windows using graphical input. The pop up windows allow a quick definition of the desired properties. Since the entry of these properties depends heavily on the tool employed and is, as a rule, self-explanatory, this will not be discussed in detail here.

Under the bottom line, a graphical specification of behavior having the properties described above can lead to a substantial increase in productivity. In addition, this method contributes significantly to the documentation aspect.