Schematic Editors:Buses,Back Annotation,Page Frames and Title Blocks.

Electrical Connections

In order to connect devices wires are drawn from pin to pin. Graphically the wires are represented by lines which may branch off but always represent the same electrical potential of a signal node. For better documentation and orientation a wire may be labeled with a signal name. Crossing of wires may lead to electrical connection, in which case the system must provide a graphical element of a junction dot. Crossing wires represent two different signal nodes as long as there is no junction dot connecting them. In some cases junction dots are forbidden so that intersections have to be drawn with an offset if a connection is wanted (see fig. 3.5d)).

Any non-labeled signal nodes will automatically be numbered by the editor. As a consequence the signal names are no longer self-explanatory, which does not ease circuit verification or debugging after simulation. The property ‘connect by name’ bears  a high risk, causing all nodes with the same label to be automatically shorted. If two wires are equally named by coincidence they will be shorted even without any graphical contact in the schematic. In PSPICE this property can be set by an extra switch and then all signals through any level of hierarchy are shorted. With the ALTERA and MENTOR system all equally named signals of one sub-design level are always shorted.

Symbolic Design Entry-0017

PSPICE and ALTERA do not provide a ‘renaming symbol’ to change the name of one signal without losing the electrical property of a common potential. MENTOR provides such a symbol ‘Net- Con’ to short two differently labeled nets without introducing any electrical functionality. Further possibilities are described in ‘Global Signals’ of section 3.2.2.

Buses

In datapath designs the same circuit function often has to be used for different signals. For example, all bits of an A/D converter have to be inverted. The editors provide different mechanisms for com- pacting repetitive parts of the displayed circuits:

• Signal buses; and

• Hierarchical designs (see section 3.2.2).

Buses are the combination of several wires to a line that is usually drawn in a wider style. In principle, the same rules are used for connecting buses as are used for single wires. A bus pin on a symbol has to become connected to a bus of equal width. The identification of the signals contained in a bus bears some risks. The designer has to carefully label the bus according to the number and the sequence of the signals in the source and the target notation.

There are two basic methods for naming a bus. On the one hand, there are implicitly indexed  signals. A bus label is followed by a range of numbers within square brackets: data[3–0] rep- resents the four signals data3, data2, data1 and data0 in exactly that sequence. On the other hand, any sequence of net names may be used when they are separated by commas without any spaces.

Another four-signal bus could be labeled a,b,c,d. Depending on the design system, one may find differing syntactic and semantic rules for the same mechanisms.

In order to branch off from a bus the easiest way is to use a T-junction or dot-crossing, which will produce the same width and signal order as the source bus. A more delicate task is forking off partial buses or single signals. The branches have to be labeled with a true subset of the source bus. Figure 3.6 demonstrates the situation: four signals, bit3 to bit0, are combined to a single bus bit[3–0]; a partial bus, bit2,bit3, branches off (with different sequence!); bit0 connects to a single wire and the internal ports D3, D2, D1, D0 of DAC4 are connected.

Symbolic Design Entry-0018

Back Annotation

Back annotation describes the process of writing values of subsequent calculations back into the schematic. Examples are the values of a DC analysis, capacitance values on output wires, logic levels, or the placement in multi-part packages such as the 74 series. Dedicated symbol attributes are prepared for such a mechanism and the resulting values get assigned to those attributes to be displayed in the schematic.

Page Frames and Title Blocks

Each page automatically has a rectangular border or frame usually containing grid information for easy location of elements on the page. The grid partitions could use numbers in the horizontal

direction (1, 2, 3, .. .) and alphabetic characters vertically (A, B, C, .. .). The title block serves to register information such as the design house, designer’s name, project title, date, and version. In addition, all editors allow placement of any kind of text for documentation. Such text will then not be relevant for any further processing step.

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