Back-end Design Tools (Physical Design):Signal Integrity Issues.

Signal Integrity Issues

Signal Integrity

Larry:

Signal Integrity measures how well a signal travels from one logic gate to another. If the signal on a wire is larger than a certain voltage threshold (say, 0.5 v.), then the gate interprets that signal as a logical "one." If the signal is below that threshold, the gate decides that the signal is a "zero." So, anything that disturbs the signal voltage level can cause an error.

Noise can reduce the signal voltage and increase the time to travel. It is similar to static on the radio and dropout on your cell phone.

Signal Integrity Analysis (SIA) tools evaluate the effect of noise (from all sources) on the signal. This includes coupling between signals (crosstalk), and other noise on the chip. The SIA tools flag danger spots and critical nets.

All these noise sources can cause errors at the receiving gate. The error can cause a momentary (soft) failure in the chip operation. Signal integrity requires complex three-dimensional models to analyze the noise effects accurately.

Signal integrity tools do this analysis and avoid or fix the problem, or notify the designer.

Nora:

Can any of these tools help my cell phone dropouts?

Larry:

I'm afraid not. The analogy is okay, but the causes are different. The cell phones are transmitting signals over miles. The chips are transmitting signals over fractions of an inch.

Voltage Sensitivity

Larry:

Electronic circuits will work over only a small range of voltage. Temperature, process variations, and noise all affect how the circuit performs. Voltage Sensitivity tools analyze the design to check that voltage is adequate all over the chip, under all conditions. Some chip operations use more current than others and this can affect the voltage at different spots on the chip.

Noise Margin

Larry:

Earlier chips worked at five volts. We reduced chip voltages to one volt to lower power and increase speed. However, the noise problems on the chip have increased.

A logic gate expects to see two distinct signal levels (high or low) at its input. Noise can cause a one to look like a zero, or vice versa. The margin between the expected signal and the threshold voltage is called the noise margin.

With five-volt circuits, a gate can still recognize a signal even with a half-volt of noise on it. However, with one-volt circuits, a gate may not recognize a signal correctly with one-half volt of noise. The one-volt circuits give us less noise margin.

Nora:

What can be done about that?

Buffers

Larry:

When a signal travels down a wire, it loses voltage due to the resistance of the wire. (This is similar to the way in which water loses pressure as it flows down a long hose.) So long wires can lower the signal strength below the receiving gate's noise margin.

Amplifying buffers can be inserted into long lines to boost the signal strength. (They add more drive power, so the decrease in wire delay exceeds the added buffer delay.) EDA tools automatically calculate where buffers are needed and insert them. Some designs require thousands of inserted buffers. Buffers are used for both timing and signal integrity issues.

Switching Noise

Larry:

When a signal switches rapidly, it can induce or couple a noise spike into a nearby wire. The coupling is worse the longer the wires run parallel and the closer together they are. Faster switching time also increases the noise.

If parallel wires (as in a bus) switch concurrently, the simultaneous switching noise effect is worse.

Clock lines also induce a lot of noise into a chip. Sudden changes in the power use can cause noise on the power bus. This noise is coupled through the power lines, the signal lines, and the chip substrate.

Nora:

Does all this noise ever get off the chip to affect other chips?

Electromagnetic Interference

Larry:

Yes, and Electromagnetic Interference (EMI) analysis tools calculate the interference created by the fast switching on the chip. EMI noise can affect other on-chip circuits, or radiate off-chip as RF interference.

It can also interfere with other system electronics such as low-level analog amplifier circuits and wireless telephones (e.g., when you can occasionally hear someone else's conversation on the telephone). We test forelectromagnetic compatibility (EMC) to ensure low enough EMI level from an IC.

Nora:

What else can go wrong?

Metal Migration

Larry:

Most solid-state (semiconductor) electronics do not wear-out, like mechanical parts. However, there is at least one important similar failure mode.

High current in a thin metal wire can actually move (migrate) metal atoms, making the wire thinner. The thinning increases resistance and delay, which may cause a timing failure. Eventually this metal migration can cause a hard failure (break or opening) in the wire.

Power lines, heavily used signal or clock wires are the most likely places for this to happen. Thick enough wires can prevent migration from ever starting. Metal migration analysis tools check the design for this catastrophic problem area.

Nora:

I didn't realize ICs could fail like that. Do the wires actually heat up and melt?

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more