Front-end Design Tools:Timing Analysis Tools

Timing Analysis Tools

Nora:

Is there any shorter way than simulation to get the timing right?

Luigi:

Yes, there are two kinds of timing analyzer tools—dynamic and static timing analyzers.

Dynamic Timing Analysis

The simulator can use known or estimated values for the wire and gate delays. It calculates the event-to-event times while the simulation runs. This is dynamic timing analysis (DTA). It can reveal potential timing errors. A timing error example is data arriving late at a register, after the clock signal.

Static Timing Analysis

In addition to simulation, there are static timing analysis (STA) tools. These move a value through the logic and uncover timing errors without using test vectors. These analyzers run much faster than simulators.

Clocks

Nora:

You've mentioned clocks a few times. How do those fit in?

Luigi:

Timing is a critical design area. High-speed electrical pulses called clocks control most digital systems.

Clocks act like traffic lights controlling when cars (signals) move, and when they wait for others. Fire trucks or ambulances (and some signals) are more critical than others.

Clock signals need to arrive at thousands of places all over the chip at the same time. This often requires moving wires around or shortening wire paths. The IC performance depends on the wiring layout of these clocks.

Nora:

What happens if a signal is late?

Did You Know?

Most digital systems use clocks (timing pulses) to keep everything in step. These are not wall clocks.

Everyone has seen marching bands on TV, at sports events, and in parades. Each member of the band moves in time (synchronized) with the drumbeat. If the beat rate is faster, they move faster.

Everyone has seen heartbeat monitors on TV drama shows about hospitals and doctors. The screen shows the electrical pulses of the heart beating (until it flat-lines and the show is over.) Digital clock pulses look very similar on a monitor.

The more frequent the drumbeat or heartbeat, the higher the frequency (beats or pulses per minute). Digital systems measure frequency in millions of clock pulses per second.

A 100-megahertz chip has a top clock rate of 100 million clock pulses per second.

Signal Timing

Luigi:

A race condition (or delay fault) occurs if a data signal arrives too early or too late with respect to the clock. The signal may not get latched into a flip-flop or register if it is late.

Signals also get delayed as they go through gates and wires. Signals may arrive earlier or later than expected (slack time). So slack times are calculated for every signal net.

Timing analyzer tools search the design for race conditions. They identify potential faults in the FE design. They identify (and sometimes fix) real faults in the BE physical design. The slack time can be changed by changing the wire lengths or inserting a buffer circuit which speeds up the signal.

Modifying the design for thousands of signals so that none arrives too early or late is known as timing closure. However, the fixing of one timing problem may cause another problem to pop up somewhere else. This can make timing closure very hard (or impossible) to achieve on large chips. One way to achieve closure is to slow down the clock rate. Some integrated tool suites do this to guarantee closure.

Nora:

But then you may not meet the IC performance requirement, right?

Luigi:

That's right.

Nora:

It seems there are tests at every level of design entry, modeling, simulation, and so on. So verification must be a really important part of design.

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