Back-end Design Tools (Physical Design):Manufacturing Preparation Steps

Manufacturing Preparation Steps

Merging Operations

Larry:

Yes, there are a few more steps required. EDA tools help do these at the IC manufacturer or foundry. The design must be merged with all the underlying standard base mask layers. Those base layers include the on-chip process test pattern, the input/output (I/O) pads, and the standard electrostatic discharge (ESD) protection circuitry.

Nora:

What does this ESD circuitry do?

Electrostatic Discharge Protection

Larry:

The Electro-Static Discharge circuitry protects the chip I/O from electrostatic voltages. Static electricity causes the tiny sparks you create when walking across a carpet. The sparks can reach thousands of volts. Static electricity may also occur when handling the chip in the assembly and packaging phases. On-chip ESD protection circuits protect the IC from being zapped by spikes up to several thousand volts.

Nora:

So that's what they mean when they say a chip got "zapped." Is the making of the mask part of the back-end?

Larry:

It used to be, but now masks are made at a few specialized mask shops, and a set of masks can cost millions of dollars!

Mask-Making Preparations

Larry:

There are several kinds of photomask machines. Some require unique data formats or handle the graphical polygons differently. The data is usually re-ordered to speed up the mask-making procedure.

Different optical techniques, such as Optical Proximity Correction (OPC), are also used for finer resolution. These require programs to prepare the chip design data files for the mask shop. (See Appendix B for more on semiconductor manufacturing.)

Nora:

So you send off the mask data and you get chips back?

Diagnostic and Manufacturing Tests

Larry:

Well, it's not quite that simple. First, we have to prove that the IC design works. The chips first need to be tested, either by the manufacturer or by a contract test provider. The design phase is not over until the first chip works. This event is known as first silicon success, and it is the crucial milestone in chip design.

Initial diagnostic testing on a new chip looks for design errors and their causes. The designers' test patterns (vectors) are used to verify the design behavior.

The first wafer needs to pass the wafer test in which all the chips are tested while still part of the wafer. If any individual chip works, then the basic design has been proved! Getting more chips working is (simply?) a process ofyield improvement. Often, the design team has a party to celebrate first silicon success.

For designs done on FPGAs, however, the design can be reworked and re-implemented in the FPGA without requiring any silicon changes, since the silicon has already been proven.

We can use faster manufacturing tests once a chip design is proven to work. These screen out chips that fail from manufacturing issues, not from design flaws. Manufacturing tests include various electrical tests and fault checks.

In chip testing we want to ensure that every gate, wire, and via gets tested. Each test pattern should check for one or more possible failures.

Nora:

How do they do that?

Larry:

Most electrical faults on a chip are quite simple. As with home electrical problems, the usual issues are shorts or breaks in the connections. The electricity is either stuck on (a short circuit), or can't get through (stuck off, a break in the wire).

Chip failures (transistor, gate, wire, via, etc.) also show up as a signal not switching as expected. The signal will be either "stuck high" or "stuck low." Not surprisingly, these are called stuck-at faults. So if the test patterns check every chip fault (point of failure), we have a reasonably thorough test.

Nora:

But how do they know they have checked every fault?

Automatic Test Pattern Generation

Larry:

Fault coverage is a measure of the effectiveness of a set of test patterns. There are tools to measure this, and the goal, of course, is 100% (i.e., every potential fault is tested).

Automatic Test Pattern Generation (ATPG) tools create sets of test patterns to improve fault coverage. ATPG has been a major research area for years. These ATPG tests usually test for stuck-at faults and may be used alone or added to the designers' tests. Being able to compress the number of test patterns directly reduces the test time and chip cost.

However, high-speed manufacturing testers (made by different vendors) do not all use the same data formats. Therefore, the design test pattern files may need to be edited, restructured, or reformatted. The fewer the test patterns, the shorter the total test time. The goal is to thoroughly check the chip with a minimum number of tests.

The testing is thus structured (by EDA tools) for quick, gross tests first, and longer, detailed tests later. This reduces the cost of testing bad chips. Other tests are added to help quickly screen out bad parts.

IC testers check the chips while they are still part of the wafer (wafer test). Bad chips are marked and discarded after dicing. Good chips move on to be "assembled" in a package, and other IC testers then check the packaged IC (assembly & test, or final test).

Nora:

So who gets the chip to work if it fails?

Did You Know?

IC chips are not repairable. So any failure, no matter how small, fails the whole chip. The chip is either a "go" or we throw it out (a "no-go"). So manufacturing fault tests are called go/no-go tests. (Note: some chips, such as memories, include redundancy to be able to use the chip even with a partial failure.)

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