Schematic Editors:Configuration of Libraries and Placement of Symbols.

Configuration of Libraries

At the beginning of a project the target symbols have to be specified. Since most systems already have pre-installed primitive libraries, the user has to configure his/her specific project libraries in the library search path.

Choice of Page Size and Editor Configuration

The choice of the page size basically depends on the target printer or plotter. Hierarchical designs should be drawn to fit easily onto a letter sized or A4 page. Other editor settings are grid spacing, snapping to grid, and measurement units ‘inch’ or ‘mm’. The grid spacing of the editor should never be larger then the minimal pin spacing of symbols because otherwise not all pins can be connected. It should also not be much smaller to prevent placing a wire only in the vicinity of pins. For details see fig. 3.17.

Any other settings, such as visibility of grid points (sometimes grid lines), non-orthogonal wiring, or visibility of certain attributes, may be set or changed at a later point in time. Those settings do not change the positions of symbols or the connecting wires.

Placement of Symbols

The chosen symbols are selected in the library browser and deposited on the page in a meaningful way. Normally the signal flow goes from left to right. All systems use a ‘drag&drop’ mechanism for symbols except ALTERA. A selected symbol is shown by its outline and gets dragged across the screen while holding down the left mouse key; upon release the symbol is dropped on a grid point. ALTERA, though, needs an insertion point defined prior to the selection of the symbol. Directly after the placement the symbol remains selected for easy rotation, flipping, or alignment operations. With a function ‘Repeat Placement’, some editors allow easy arrangement of symbol arrays.

Undo, Redo

As with text editors, the last commands may be corrected by undo or redo functions. Modern editors allow setting of the undo depth.

Wiring of Symbols

In PSPICE and MENTOR the drawing mode has to be set explicitly by a command (Draw Wire). In the ALTERA system the mode switches automatically when the mouse cursor moves over a pin or wire end. The wire can then be drawn by pressing the mouse button and dragging to the target point. Wire junction points are automatically added when a wire begins or ends on an existing one.

PSPICE uses two different objects for a wire and a bus. ALTERA and MENTOR differentiate them only by the line width.

Signal Labels

Normally the edit mode of a signal label is entered after double clicking on a wire or a bus.

Setting of Attributes

The appearance of a schematic may be influenced by editing some properties and attributes after all symbols have been placed and wired up. PSPICE allows the visibility of basically any attribute to

be set. The instance names may also be changed instead of using the automatic numbering system. Often it may be necessary to move part names, instance names, or signal names to more adequate places.

Pan and Zoom

Pan and zoom are graphical commands to place the desired selection on the screen. Usually there is also at least one function to fill the screen with the complete schematic in an optimal way.

Correcting the Entry

In order to change errors during design entry, there has to be a set of graphical edit commands as they are known from text editing:

• Selection (highlighting) of one or several ele- ments (wires, symbols or text);

• Moving selected elements;

• Copy, cut, and paste;

•

Problems may arise during correction when the function ‘rubber banding’ is switched on. With that function, connections remain in place even when symbols and wires are moved about. In those cases, unwanted shorts may incidentally occur which should be repaired immediately by an undo function. An example is shown in fig. 3.18.

MENTOR treats signals shorted in such a way during an edit process by a very special method. Those signals are not shorted (and not renamed) but a special warning symbol is placed at the cross- ing (similar to a ‘No Parking’ sign).

Schematic Checking

Most topological and electrical errors of a schematic can be found by an ERC (Electrical Rules Check). In the ALTERA system a special switch, Design Doctor, has to be turned on during the compilation run. A netlist may only be created after all errors have been removed. An extremely helpful function is localizing an error in the schematic by back annotation. For that purpose an error message is double clicked and the schematic page is brought forward with the cursor placed at the error.

Printing and Plotting

The pages of a design should be printed or plotted for documentation purposes. The possible options may have to be combined carefully to obtain satis- fying results:

• Print or plot ‘print/plot only selected area’ or ‘print full page’;

• Print/plot on a single page or divide the circuit into segments for several pages.

Placing Schematics into other Documents

In order to place schematic drawings in docu- mentation systems, one may ‘print’ them to a file in a PostScript format (*.eps for Encapsulated PostScript). The result is a graphic file in vector format. Vector graphic files may then be imported into programs such as CorelDRAW!, Micrografx Designer or Visio. Subsequent operations may change line thickness or colors. The resulting file would be of *.eps format again to be read into word processing programs. The screen content may also be grabbed as a pixel bitmap. In that case a high resolution screen must be used in order not to lose any lines due to interference. A very suitable format is .png (portable network graphics) which stores such bit maps in very small files. Important is a reduction of the number of colors to the absolute minimum. Schematics can usually be well displayed with two (black and white) or 8 colors.

Special Characteristics of Schematic Editors

Even if the basic tasks of schematic editors from different suppliers are all the same, each program is equipped with some individual properties which are only found in a few or even only one of the programs. Some of the characteristics worth men- tioning are described here.

Library Manager

A library manager is a set of tools which allows the administration of graphical and non-graphical in- formation of the involved libraries. The necessary functions are the export and import of symbols in an ASCII format. Such a mechanism may be necessary to convert libraries to other versions of an editor, for example when the binary symbol format has been changed.

The PSPICE Schematic Editor product of OrCAD offers such functions to the user. ORCAD’s Capture product even allows access to libraries through the internet.

ALTERA and MENTOR do not make these tools available to the end user.

Parameterizing

The original Berkley version of SPICE had already provided the keyword PARAM, which allows the value of device parameters such as size, resistance, or capacitance to be controlled. This mechanism has been carried over into the graphical editor of PSPICE. Parameters may be given global assignments which are evaluated at each instance of a graphical object.

For example, instead of assigning a fixed value to a resistor an expression may be used which contains a symbolic name of a parameter. Two resistors may have the assignment {3 * Rbase} and {12 * Rbase}. The global parameter Rbase may have a value of 10 k leading to final values of 30 k and 120 k for those two resistors.

In a similar way MENTOR provides passing of parameters in its Falcon Framework programs by using the scripting language AMPLE.

ALTERA uses such a mechanism only for passing information down to text files, such as AHDL (ALTERA High level Design Language), VHDL or Verilog but not to graphical elements.

Scripting Languages

On the basis of the AMPLE language MENTOR allows access to almost any part of the design data base. AMPLE scripts may be used to configure programs and data files. In a similar way AMPLE is also used to automate the generation of symbols, simulation stimuli or layout elements. For the future a C based language has been announced. Starting with versions PSPICE V9, ORCAD wants to offer a scripting language which is similar to Visual Basic.

Engineering Change Order (ECO)

The ECO method provides a mechanism to follow up design changes from the schematic to other con- secutive programs in the design flow. During PCB design the Forward ECO method is well established. Incremental changes in a schematic have to be marked in the final layout. Small changes may still be done by hand without re-running the time consuming complete Place&Route procedures.

The Backward ECO method works in a similar way. Changes to the connectivity, to names or devices on the layout level are fed back into the schematics. Thus a consistent set of design data can be kept through all design steps even if the changes happen with long intervals of time be- tween them.

Stroke

The MENTOR design systems provide a method of assisting the user when entering commands. Instead of using key strokes or menu clicks, mouse movements are interpreted as commands. While pressing the middle mouse button, the total mouse movement is evaluated by dividing the area cov- ered into nine sections. The relative sequence of movement is then interpreted as a command. Fig- ure 3.19 shows the sequence of the most important commands.

Machine-generated Schematics

When using synthesis tools a behavioral, an RTL (Register Transfer Level) or a structural text description is optimized and mapped to the library

elements of an FPGA or an ASIC library. In any of those cases the result is a form of ASCII netlist. Under certain conditions it may be desirable to visually check the resulting logic. For that purpose, some design systems provide built in schematic generators.

Such a generator needs access to the symbols of exactly those library elements that are referenced in the netlist. The logical content of the library has to be reproduced exactly. In addition, the generator has to produce the topological arrangement of the circuit. Primarily a placement of non-overlapping symbols and wires has to be achieved.

A manually drawn schematic may use the neigh- boring relationship of symbols in order to increase the readability for humans. Such a characteristic is usually not found in generated schematics. They may be logically correct but are not always well readable. Figure 3.20 shows an example from the MENTOR system. A VHDL description has been optimized and mapped to the cells of a MIETEC ASIC library by a synthesis run. The reader can easily see which logic elements have been used, such as gates and flipflops. He also obtains an impression of the number of wires and buses used, but the logical function is not necessarily apparent.

Netlist Generation

Netlists establish the connection between the graphical or textual design entry and the subsequent design steps, such as simulation and implementation. Before generating a netlist, the entry has to be checked for errors and inconsistencies. In an ERC (Electrical Rules Check) run, for example, multiple instance names, unconnected inputs or shorted outputs may be detected.

The structure of different types of netlists is de- scribed in chapter 8. Normally a flat netlist is generated. In hierarchical netlists the hierarchy information has to be preserved for device names and node names by the use of path structures.

Any digital or analog circuit gets translated into a SPICE netlist in the PSPICE system. It is a device oriented format with positional signal assignments (see section 8.1). The SPICE netlist contains con- trol information in addition to the circuit information. Model definitions for simulation can be found directly in the final SPICE list. Such a combined control list may of course also be written by hand and fed into the simulator directly. In that sense the graphical entry is one way of generating a structural netlist. Examples, partly with parameters and control statements, can be found in lists 3.3 and 3.5 of section 3.4.

The PSPICE system also supports the design of printed circuit boards. For that purpose a different type of flat, non-hierarchical netlist is used. The format uses a qualifier .nfl and is basically node oriented. An example is shown in list 3.4. This format also has to carry the socket names and foot prints to be used for the drilling mask.

The ALTERA system feeds any design entry to the synthesis tool. As a result the user sees a netlist using the syntax and semantics of ALTERA’s pro- prietary design language AHDL. In theory such an output may be used directly as an input again. Nevertheless, it is a structural list using only the available primitives of the target CPLD. Basically only the following elements are used:

• INPUT, OUTPUT, NODE;

• NOT, AND, OR, EXOR;

• FLIPFLOP.

The AND/OR terms do not directly represent single logic devices but they get mapped to the PAL (Programmable Array Logic) or SRAM based logic cells in the ALTERA CPLDs.

An example is shown in list 3.1 (see section 3.4) where the following short forms have been used:

The MENTOR system generates the netlists during the ‘Viewpoint Generation’ design step. The netlists are an integral part of the Framework and are not meant to be accessible by the user. For a gate level simulation with a VHDL simulator a

truly structural, hierarchical netlist description is created. In this case it does not matter if the source was a schematic with VHDL views behind the symbols or a synthesis run from a RTL description. Lists 3.6a to 3.6d in section 3.4.4 shows such a VHDL netlist.