Back-end Design Tools (Physical Design):Extraction and Timing Analysis Tools.

Extraction and Timing Analysis Tools

Larry:

Once placement and routing has been done, all the transistor and wire physical dimensions are known. Extraction and analysis tools use these dimensions to calculate key parameters.

Parameters include things like transistor size, wire thickness and length, and effects from nearby wires. (These were just estimated in the FE design.)

Some of these computations are very complex, involving two- and three-dimensional models.

Delay calculators use detailed models to calculate the critical signal delays down each path. They take into account the wires, transistor drive, and number of gates driven. There are several "standard" delay models in use.

The calculated parameters are entered into the design files. The dynamic and static timing checks are rerun based on physical data rather than on estimates.

Static Timing Analysis (STA) tools calculate all the gate and wire delays using agreed-upon delay models. They compute minimum, maximum, and average delays, and positive or negative slack times. Potential problems are listed for designer correction. STA is used in the FE design as well as after layout.

One way to speed up a critical path is to insert a transistor buffer circuit. This drives the signal wire faster. Inserting a buffer changes the layout, however, and some tools can do this automatically. Of course, any parameters in the affected areas need to be recalculated.

Dynamic Timing Analysis (DTA) tools simulate the chip operation with estimated delays (in the FE). They use accurate physical layout delays (in the BE). DTA tools may catch some timing problems which the STA tools miss.

Timing Closure is the procedure of finding timing problems, fixing them, and rechecking the design. Sometimes fixing one problem creates others, which then need to be fixed. With luck, the number of problems continues to decrease, eventually to zero.

However, for some methodologies there is no guarantee that closure can be found. Lack of closure can cause endless project delays and even complete failure. A picture of this is just like verification—test, find a problem, fix it, and retest. Only now the fixes involved physical changes as well.

Nora:

It sounds complicated. Does it get frustrating?

Larry:

Well, the timing calculations are complicated, that's true. (That's why we use EDA tools!) You're right, it can be very frustrating. And now we have even more factors to check to achieve design closure, such as signal integrity.

Nora:

What is signal integrity?

Did You Know?

Delays are always critical to a chip's performance. The longer the delays, the slower the chip will run. Delays may also determine whether a chip operates correctly. Just getting the signals to the right place is not sufficient. They also have to get there at the right time.

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