Schematic Editors:Connections in Hierarchical Designs

Connections in Hierarchical Designs

Sub-designs are most easily connected through the block symbols to a higher level by port symbols. In the underlying module the input and output signals are connected to input and output port symbols. Just like the off-page symbols, such I/O ports need distinguishable, unique names. Schematic editors usually have built-in symbol generators for such block symbols. Thus the I/O port types and names are converted to the corresponding pins of the

block symbol. When the sub-design contains a bus the block pin will be of bus type with a pin name that is equal to the bus label.

Numbering of Devices and Signals

At the lowest level of hierarchy only primitive symbols are found; these have to be distinguishable. An inverter in sub-design C will switch at different times when it is instantiated in TOP_BlockC1 than in TOP_BlockA_BlockC2. In order to differentiate between physical devices, the instance name of an individual device gets extended by the hierarchical path name. Different editors may use different separation characters. PSPICE uses an underscore ‘_’ like this:

The signal names are handled in a very similar way. A signal s1 in Sub-design C will become TOP_BlockC1_s1 in the first branch while it is called TOP_BlockA_BlockC2_s1 in the second one.

Global Signals

Next to the local signals, global signals are found which will be connected directly through any level of hierarchy. Besides supply nodes, there are also clock and reset signals belonging to that group. PSPICE provides symbols, such as ‘Bubble’ and ‘Global’ for that purpose. ALTERA uses an im- plicit ‘connect by name’ mechanism for every level. Signals have to be connected by explicit I/O- symbols between any level. MENTOR provides a symbol, ‘Global’, for clock and reset signals. Connect-by-name is also restricted to one page or one level only.

Views

The view of a block is a mechanism for represent- ing different types of description behind a symbol. A Schematic View is used to define the circuit be- hind a symbol as a graphical schematic drawing. A VHDL View would describe the content as VHDL text. Depending on the type of VHDL description, there could be behavioral, RTL, or structural text. In any case, a synthesis compiler is then needed. The text has to be converted into a structural netlist which may be combined with other netlist parts from schematic entries. Such a mixed entry can be seen in fig. 3.10. It shows the hierarchy tree of the ALTERA system where graphical files (.gdf) are mixed with textual files (.tdf). Such a scheme

allows a high degree of complexity. Any graphical or textual sub-design may be referenced in any higher level graphical or textual block. Therefore, tools are provided for creating symbols from either  .gdf or .tdf files and also a mechanism to create so called include files to be created from either .gdf or .tdf. Thus a view is an abstract form of modeling a design block.

Soft Macros

Soft macros are pre-designed flat or hierarchical circuits with a corresponding block symbol. The underlying design is usually drawn as a schematic of primitives from a specific library on a specific editor. As a consequence, soft macros are very dependent on technology and design tools. They may be ported to other design systems if the tool supplier offers the exchange of schematics and symbols as a defined product feature.

Many systems provide the functionality of the 74 device families as soft macros. In such a case the schematics behind 74 device symbols are of- ten drawn with the primitive INV, AND, NAND, OR, NOR, and DFF symbols of the implementation library. For simulation and implementation purposes the soft macro will be ‘flattened’ into a netlist of primitive functions. The structure of the soft macro is usually completely lost in such a flat netlist.

This also shows the weakness of soft macros. The final structure and the timing behavior depend only on the available primitives and the mapping mech- anisms. In any case, the function of the soft macro has to be carefully verified in the final design.

Design Style

The two methods, hierarchy and views, allow complex designs to be created with relatively little effort, which is especially necessary for FPGA and ASIC designs. A preferred method is to use a graphical top level in which one block symbol is placed next to all input and output pads. Such a style guarantees the overview over all the physical I/O-pins.

The second level may represent the partitioning structure of the design as a block diagram. The blocks are then single units which may be designed separately by different people. A top down style requires each function to be refined down to the final structural level. A high level function may thus be described first in a behavioral manner and verified by simulation before the refinement into the final structure.

On the other hand, a bottom up approach combines functional groups to more abstract blocks after thorough structural verification. The method gets repeated until the top level is reached. In practice, a combination of both approaches may be used which usually get applied alternately.

Assignments, Properties, Attributes

All modern editors build up the designs in an object oriented manner. The basic concept will then be applied systematically to create possibly very complex designs. One of those basic concepts is the mechanism of assigning a well defined set of properties to the design objects. The names which are used may be ‘property’, ‘assignment’

or ‘attribute’, but they basically all use the same methods: attributes with names and value assignments. A very strict implementation is found with MENTOR. The types of attributes and the range of values are always checked automatically.

Some attributes are used in exactly the same way with all editors: the symbol name is the value of an attribute ‘Symbolname’. In a similar way, the attributes ‘Instancename’ and ‘Pinname’ are used for instance names and pin names. Even if the basic mechanism is very similar, editors may differ immensely in some detail of handling.

ALTERA places the assignments for further pro- cessing in the following way. Figure 3.11 dis- plays a partial zoom of a schematic with a symbol CSFIFO and some attributes which have been switched to ‘visible’. The assignments are dis- played in little dotted boxes next to the symbols, wires or I/O symbols. Besides the already known attributes ‘Symbolname’, ‘Instancename’ and ‘Portname’, others are found, such as:

• Timing: assignment of a timing constraint on a specific wire (signal);

• Clique: grouping of certain logic blocks in or- der to keep a short critical path;

• Pin: assignment of an I/O port to the pin of the chosen package.

Further possible attributes could be:

• Probe: alias name for a signal hidden deeper down in the hierarchy;

• Device: placement of the logic in a certain de- vice if the complete design has to be partitioned over several physical CPLDs;.

• Logic Options: choice of optimization switches for logic synthesis.

Another class of attributes are parameters of a block symbol. They will be passed down to the underlying HDL (High Level Design Lan- guage) text. In Figure 3.11 it can be seen that the number of words of the FIFO is set to 16 (LPM_NUMWORDS) and the data width is set to 4 (LPM_WIDTH). This method applies to all AL- TERA LPMs (Library of Parameterized Modules). A user may apply the same method of passing parameters to self-written HDL modules.

In PSPICE the user may configure the attributes more freely. Figure 3.12 shows the dialog box for editing the attributes’ names and their values used by the 7410 NAND3 symbol. The standard attributes of this symbol are:

• PART: symbol name;

• MODEL: pointer to the logic and timing model of this device. Alternatively, this could also be a pointer to a textual subcircuit description;

• REFDES: short for reference designator. It is used to assemble the placement name. In the library symbol REFDES has the value ‘U?’. When the symbol is placed, the ‘?’ is replaced by a running number (a ‘2’ in fig. 3.12). Ad- ditionally, the assignment to a physical place in the final package can be seen (here it is U2A with the pins 1, 2, 13, and 12). REFDES and the pin numbers are thus used for back annotation;

• TEMPLATE: the value of this attribute con- tains the formatting commands for the netlist line of this part;

• IO_LEVEL: assignment of the analog interface when a mixed signal simulation is started;

• MNTYMXDLY: setting of method for the calculation of minimum, typical and maximum propagation delay times;

• ipin(PWR): assignment of the global hidden digital supply node $G_DPWR;

• ipin(GND): assignment of the global hidden digital ground node $G_DGND.

For each attribute the type of display (What to Display) may be set, as well as display formatting (Display Characteristics). A very important feature is whether or not the attribute may be changed by the user when placed in a design (Changeable in schematic).

For the selected attribute REFDES only the value (Value only) will be visible and the user may change it in the schematic. The attributes PART, TEMPLATE and the two ipins cannot be changed in the schematic since they represent basic data of this library element. The user may add attributes with new names and values to a symbol. With those he/she may, for example, pass more data to a netlist or to models. For that purpose the value of an attribute in the formatting TEMPLATE string can be used with the prefix @. PSPICE neither checks the type of attributes nor a violation of the value range.

In PSPICE the pins represent a sub-class of restricted symbols with pre-defined properties. They have a name, number, type, and display property such as orientation and visibility. The attribute pin number is used for back annotating the part assignment in a package. A further attribute ’ERC-Type’ may be set to control subsequent ERC checking (Electrical Rules Check).

A pin may be of one of the following types: input, output, don’t care, highZ, bidir, open collector, open emitter or power. According to the type, the permitted method of connection can be checked by the editor or netlist converter. For example, two pins of type output are not allowed to be connected. Two inputs do not need that restriction. This mechanism is valid not only for digital designs but also for analog and mixed signal designs. Netlisting is done according to the rules of the SPICE netlist which has the character of an industry standard. For analog cell designs the width and length of MOS (Metal Oxide Semiconductor) transistors may be entered in the instances allowing individual sizing of the devices. Thus, the W- and L-attributes can be set in the schematic and are passed through the TEMPLATE down to the MOS-models.

In the MENTOR system, the strictest type-oriented methodology of attributes is found; they are called properties. Only the following objects may be associated with properties:

• Symbol icons;

• Instances;

• Nets (nodes);

• Pins;

• Comments;

• Frames.

Each property may be of one of the following types:

• Text string;

• Number;

• AMPLE expression;

• Triplet (min, typ, max timing values).

Figure 3.13 shows the so called Component In- terface of the MENTOR system. It displays the properties belonging to a symbol (see also the MENTOR symbol editor in fig. 3.16).

Symbol Libraries

Symbols are organized in symbol libraries. Usu- ally one library is stored as one file. More details concerning the content and usage of ASIC libraries is described in chapter 17. Library files have to be configured for an editor before symbols are ready to be used in schematics. Each editor then has distinct mechanisms of handling symbols.

In PSPICE the configuration is accomplished by

• entering the library name in an options menu including the complete path; or by

• entering the library name relatively to a separate path entry (Library Path).

Using the second method, libraries can easily be exchanged by simply changing the path name.

Symbols with the same name may exist in different libraries. Thus, the sequence of library name entries determines which symbol shall be used: it is always the first appearing symbol.

This control mechanism allows the exchange of, for example, ANSI and IEC symbols by just re- versing the order of library entrances.

PSPICE has an easy to use library browser for se- lecting the symbols. All symbols of the configured libraries are displayed in a list sorted in alphanu- merical order. Next to the symbol name and a textual description of the function the user can also visually check the symbol’s icon in a graphical preview. By providing three further mechanisms the searching process is made easier when large numbers of symbols are configured:

• Search by name with replacement character

• Search by keywords in the textual description;

• Search in the single libraries.

In PSPICE there is no method of freezing library elements. A symbol placed in any schematic may be edited by any user with the symbol editor. Such openness is potentially dangerous because the position and attributes of pins are extremely sensitive. A wrongly moved pin can seriously disturb the function of the circuit.

ALTERA uses a similar mechanism, although library elements exist in the same directory as de- sign files of a project. Symbols are also prioritized by sequence. The following files are the basis for symbol placement:

• The current project directory is searched first;

• Then a configured list of ‘userlibs’ is used;

• At the end the search continues through the pre- configured system libraries ‘max2lib’.

The selection is only done by scanning the symbol lists in those directories. ALTERA does not allow editing of primitive symbols for security reasons.

In the MENTOR system the libraries are con- figured by a script containing all symbol names. Then a library palette is available in the graphics editor. An example with a MIETEC ASIC library

is shown in fig. 3.14. Four symbols have been selected and placed.

Symbol Editors

The use of a symbol editor has two goals:

• to design new symbols; and

• to update existing symbols, especially those generated automatically.

A symbol editor is a program which works in a way very similar to the standard editor except that the design objects are symbols and not electrical schematics. Creating a symbol can be done from scratch or by copying and renaming existing sym- bols.

Each system provides a mechanism for automat- ically generating symbols from circuit modules. The size of such a normally rectangular symbol is usually determined by the number of input pins (usually on the left edge) and the number of output pins (on the right edge). In any case, the symbol has to be placed in a library in the library path. In order to adapt the symbol to specific needs it

may then be changed in the symbol editor. The same restrictions regarding the sensitivity of pin positions still apply as to any other symbol.

The important drawing elements of a symbol editor are:

• Elements for the icon, such as lines, rectangles  and (partial) circles;

• Pin symbols of normal, inverted (with inverter bubble) or clock (with clock triangle) type;

• Text for labeling;

• Bounding Box, which determines the selection area;

• Origin, which becomes referenced in the schematic. All the symbol coordinates are only relative to the symbol origin.

Figure 3.15 shows the window of the PSPICE symbol editor. In the drawing area elements may only be placed on visible grid points. Any element can be selected and edited by cut, copy and paste. The NOR4 symbol has normal input pins whilst the output uses an inverting pin. In any case, the little cross is the point of contact for a wire in the schematic. The symbol icon has only a

descriptive character so that a user can recognize or identify the symbol. The netlist generator only needs the wire connection to a pin. An attribute editor for all the symbol properties is also built into the symbolic editor.

The ALTERA symbol editor is much simpler. It is limited to updating automatically generated symbols. The user may change the size of the rectan- gle, the bounding box, and the position of the pins.

Of course, type and size of the selected text font may also be adapted.

MENTOR also provides a symbolic editor (SYMED) for changing appearance and properties of symbols (see fig. 3.16).

Edit Functions

This part describes the generation of a schematic with its fundamental steps. The concepts used  have been described so far in chapter 3. As a result some examples are presented in section 3.4. Basically the on-line help systems are well enough established so that the use of printed manuals may become almost obsolete.