Schematic Editors:Examples of Schematic Entry and Design with Logic Symbols

Examples of Schematic Entry

This section describes examples of various design styles on different design systems. The examples demonstrate the concept of design entry introduced in the previous sections. The symbols described in Appendix A may be used to translate between IEEE and IEC symbol icons. A list of the different types of examples is given in table 3.1.

Example of an FPGA/CPLD Design

Design with Logic Symbols

This example describes a hierarchical circuit of a 4 bit adder on the ALTERA design system (see fig. 3.21). It only consists of primitive symbols XOR and AND2 at the lowest level. This circuit is represented by a block symbol ‘half_add’. Two ‘half_add’ block symbols and an OR2 primitive are placed on the second level. It leads to the next level ‘full_add’. On the top level this ‘full_add’ symbol is placed four times and the input and output symbols define which nodes are to be connected externally through the device pins.

At the time of compilation, the ALTERA system passes pin names to the Waveform Editor where stimuli for a simulation have to be supplied to the inputs. The sequence of output signals gets displayed after the simulation run.

The following details should be noted:

• The buses Ai, Bi and Sumi consist of 4 bits each. The ‘Connect-by-Name’ mechanism produces the necessary netlist;

• The supply pins VDD and GND are not drawn. They get implicitly generated and connected to the corresponding pins of the FPGA/CPLD package;

• The three graphic files are stored as .gdf files. The top level file name ‘add4_log’ is also the project name of the design;

• The netlist of this circuit has an internal binary format which will be used by the synthesis pro- gram of the compiler. The result is an optimized structural list in ALTERA’s AHDL format. It references only primitives that can be implemented in ALTERA chips (see list 3.1).

Variation: LPM Function (Macro)

A 4 bit adder may also be created by using a pre- defined LPM (Library of Parameterized Modules) function. A parameterized AHDL description can be found behind the symbol LPM_ADD_SUB. The parameters are set in such a way that the same function as ‘add4_log’ results (see fig. 3.22). The AHDL macro text gets converted into a structural AHDL netlist in a similar way as the symbolic entry before. Because the adder is now processed based on the adder function of the macro, the circuit may become 30 % smaller but also a bit slower. The I/O pins and the simulation stimuli are the same as for ‘add4_log’

Variation: AHDL Behavioral Description

The language AHDL also allows behavioral constructs, for example the addition in the form of a

Behind the symbol ‘hdl_add’ lies the AHDL text from list 3.2. The symbol replaces exactly the adder symbol from Figure 3.22. The width of the operands is extended to 5 bits because the add operation needs the same bit width for the arguments [3.2]. The round brackets establish the signal bundles. This variation leads to the same results during logic simulation as the other two, although the netlist may look different. In the same way the use of logic resources and the resulting delay times may differ. It is left to the user to select the most appropriate solution for his purposes.

Printed Circuit Board Design

A relatively simple one-transistor amplifier stage has been chosen for this example. The DC operation point is stabilized with the resistor RE and still has the full AC gain owing to the capacitor CE (see fig. 3.24a). Using the PSPICE schematic editor, a core circuit can be drawn to be used for analog simulation as well as for a printed circuit board layout. For that purpose, a block symbol ‘tr_amp’ is created and stored in a symbol library. The block symbol of fig. 3.24 has been edited for its final appearance.

Analog Simulation

In order to verify the function of a circuit with an AC or transient analysis the following elements have to be placed around the core circuit (fig. 3.24b):

• voltage supply (VCC and GND);

• signal source (including source resistance); and

• load impedance (only resistive in this case).

These elements should not appear on the PCB since they become connected through the interface plug (fig. 3.24c). The marker symbols in the core schematic only serve to make signals visible in simulation. They are ignored for the implementation. List 3.3 displays the corresponding netlist for the analog simulation. All circuit elements have been automatically extended by a prefix (see also chapter 8). The supply voltage VCC thus becomes V_VCC.

The node names of automatically named signals such as ‘$N_0002’ can easily be recognized. The netlist has become flat, although the hierarchical path information is still present: the base node of transistor BC550 is now called HS1_VB. The name of its instance, ‘HS1’, has been added in front of the node. The device values have been entered directly (not parameterized). The resistor R1 has a value of 120 kOhm, for example. The signal generator Vgen is a sine wave source with an amplitude of 20 mV at 20 kHz. An AC simulation reveals a gain of 45 dB in a frequency range from 50 Hz to 10 MHz.

PCB Layout

The core circuit only consists of discrete devices, each with a specific foot print for the PCB lay- out. The pin numbers, as they are visible in the schematic, represent those of the foot print. The top level PCB diagram (fig. 3.24c) contains the additional connector so that the PCB may be sup- plied. A special PCB netlist has to be generated for the subsequent Place&Route program.

List 3.4 shows the corresponding PCB netlist for the program PCBOARDS. It is a node oriented format (see chapter 8). All capacitors use the same foot print CK05, which of course is not generally the case. The resistors use a foot print RC05. Similar formats exist for many other PCB programs.

 

For this example the design of a 1-bit adder cell for an ASIC library based on CMOS transistors has been chosen. In principle this PSPICE schematic serves the purpose of finding the optimal size of each transistor and of characterizing the final circuit with respect to delay times and power supply. The drawing may also be used to carry out a comparison between the schematic and the extracted cell layout. Such a comparison is called LVS

(Layout Versus Schematic). The layout design is done in full custom technique; in other words, all by hand in order to get a very compact cell.

The basis of the design (fig. 3.25) are logic equations which can be derived from the adder truth table.

 

For COUT a two stage logic is used with a following inverter in order to compensate for the inverting behavior of a single stage. For SUM the result of COUT is also used which leads to a three stage implementation.

The circuit uses n-channel and p-channel MOS- FETs. The symbols do not connect the bulk contact explicitly. All bulk contacts of the n- channel transistors are implicitly connected to node 0 (Gnd) and those of the p-channel transistors are connected to the Vdd node. All the transistor symbols carry parameters for width (W ) and length (L) which can be set individually per transistor. The length parameter L has been switched ‘not visible’ because it is set by the global parameter L to 0.8 μm. The value of W is set to ‘visible’. It becomes adjusted so that the resulting width for n-transistors in series is about 2 μm. In order to obtain similar delay times for rising signals, the effective width of p-transistors gets set to 5 μm.

The gates of the input transistors are connected to the input signals A, B and CIN (see fig. 3.25, upper left) by ‘Connect-by-Name’, in order to keep the overview of the schematic. The capacitors in front and behind the output inverters represent the wire and load capacitance. Once the final layout has been extracted, the exact values have to be fed back into the schematic for a precise (after layout) characterization.

In Figure 3.25 a symbol called ‘Supply’ has been placed in the upper right hand corner. Three parameters are passed to the simulation so that the characterization limits can easily be varied:

• Temperature Tjct, which is used as a global parameter for all devices in PSPICE;

• The supply voltage Vsupply. This is the value of a voltage source connected to the node Vdd; and

• A parameter ‘speed’ to vary the strength of the CMOS transistors through their model parame- ters. The range of values for speed is:

−1 = slow, 0 = typical and +1 = f ast.

In the example the values have been set to 80 ◦C, 4.5 V and −1. Thus, the longest delay times will result.

Standard Cell IC Design

This example shows the shift register schematic for an IC design with standard cells supplied by the semiconductor manufacturer MIETEC [3.6]. The top level ‘shift4’ contains all the necessary I/O and supply pad symbols next to the block symbols ‘shift1’. The basic schematic of ‘shift1’ contains a flipflop FD2 and a multiplexer MUX21 for switching from serial to parallel data entry. The schematic of fig. 3.26 can be used in this form for logic simulation as well as for the IC Place&Route program.

Since a VHDL simulator is used for logic simulation (in this case, ModelSim), the schematic gets transferred into a structural VHDL netlist. List 3.6a shows the Entities and the Architectures of this hierarchical design.