Trends:EDA Design Environment Trends.

EDA Design Environment Trends

EDA is evolving rapidly to address the many new design issues facing the chip designer. We mentioned a few of these issues previously. The trends associated with the overall design environment include:

  • Integrated Design Suites

  • Run-Time Control

  • Distributed Design

  • System Design Links to Chip Design

Integrated Design Suites

Design tools are moving from (possibly incompatible) point tools to integrated suites of compatible tools. Some integrated suites simply use a compatible data transfer format to move data from tool to tool. Others use a common data structure or database to allow tools to share access to common data.

Interface formats for files or data may be proprietary or non-proprietary, open or closed. Proprietary means a vendor owns and controls it. Non-proprietary means the format is published and available to the public. Open means that it is free or for sale to the public. Closed means that it is available only with tools of the vendor.

Run-Time Control Tools

A design flow involves many tools, many steps, and many files. Every change to a file requires a revision number change to the file name. After a design error is detected and fixed, many related files may need updating as well. (Very often, fixing one error affects several files. Any steps we previously ran may also need to be rerun after a design file is changed.)

With all the interruptions to fix errors, it is easy for the designer to lose track of where he is in the design flow. Where are we in the flow? What is the state of the design? Which files were not affected, which files need to get updated, and which design flow steps need to be re-run? These issues are called run-time control.

Increasingly, design groups are using EDA run-time control tools. These tools include features that guide an engineer through the design flow. They include automatic revision control and tracking of files (possibly) invalidated by a design change. They reduce errors from the inadvertent mistyping of a file name.

Some tools handle automatic launching of a tool and its associated data, parameters, and output files. The tools provide automatic iteration tracking, display a history log of all the design steps and files involved, and so forth.

Distributed Design

EDA tools are evolving to support design teams separated by time, geography, language, and culture. Some issues include sharing enormous design data files, revision control, and backup.

Backup is particularly important since a damaged or lost file is very costly. Re-creating a file requires a great deal of work. The designer may have to repeat many steps in the design flow to re-create the lost file.

Other distributed design issues are security and fast file transfers (both incremental changes and whole files). Video-conferences, net meetings, and long teleconferences supplement the non-EDA side of the challenge.

System Design Links to Chip Design

Traditionally, system engineers do electronic system level design and chip designers do IC design. They exchange information manually, since their tools do not communicate.

However, several groups are trying to connect system level design directly to chip level design. Some emerging system level design languages link directly into the chip design system. These include extensions of the C and C++ programming languages, or the Verilog HDL. They are competing to be recognized as a standard.

Other groups are trying to develop a high-level, executable specification language for either hardware or software. One could create hardware description code or software code directly from the design specification. Related work includes ways to describe system design constraints (such as size, power, or speed).

Did You Know?

Some system designers prefer using a programming language to describe the system. Others prefer a hardware description. There are heated debates over which is the best approach.

Their preference tends to follow their experience: C programming experience, or graphical and HDL experience.

Hardware designers are used to thinking about concurrent systems, where operations are going on in parallel. In contrast, most programming languages are inherently sequential. Therefore, most programmers have learned to use a sequential design approach (even if a language has recent extensions to support concurrency).

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more