Trends:EDA Tool Trends

EDA Tool Trends

Tool trends include:

  • Design Closure

  • Formal Verification

  • Design Repair

  • Design for Test

Design Closure

The point when all open (unsolved) design problems are closed (fixed) is called design closure. (This is similar to unsolved crimes—the "case" is open until the criminal is caught. Then the case is closed.)

With DSM chips, the various design problems interact. Fixing one problem may cause a new one somewhere else. For example, to solve a thermal problem the designer may have to lengthen a signal path. The longer wire may increase a critical delay, causing a timing failure. Design closure may thus take a long time, with no guarantee it can even be reached.

New tool suites are attempting to balance and optimize interacting problems concurrently instead of sequentially. Some individual tools now estimate physical design issues earlier in the design flow, to avoid or sidestep the problems before they arise.

Formal Verification

As design complexity increases, verification becomes more time-consuming and expensive. Some design entry languages support notes from the designer about the design intent, i.e., what the design should do and what it should not do. These expectations (properties) are inserted into the HDL code (assertions) or are provided as a separate file.

Then a formal verification program can check the design for consistency with the design intent notes. The formal check is quick and thorough and can catch some errors that simulation does not.

Design Repair

Some BE tools can correct design rule failures automatically as well identify them. Previous tools could flag the problem, but the designer had to fix it manually. Automatic repair really helps when a tool finds some 10,000 instances of a physical design rule error (e.g., a physical spacing error on a transistor which is used thousands of times in the chip).

Design for Test

When chips were simpler, designers often left the testing up to the manufacturing test engineers. There is more interest in Design for Test (DFT) as the cost of testing increases. DFT requires the designer to plan for all the testing required from idea through manufacture.

The designer must design-in support for all the testing, right from the beginning. Several EDA tools are available to assist with DFT approaches.

Built-in Self Test (BIST). This uses a set of test patterns to test the chip at speed. The patterns are generated on the chip itself. As test time and equipment become more expensive, BIST has become more cost-effective. Logic BIST tests the logic blocks. Memory BIST is used for the self-test of memory blocks.

Automatic Test Bench Generation. This helps the engineer easily create tests. The final verification of the design is only as good as the test cases developed. Manual test generation is tedious and error-prone. Test bench tools provide a whole environment to help create, order, and run tests.

Testability. More transistors and functions (complexity) require more test patterns to test. The time and cost to adequately test a chip are increasing dramatically. Analog and RF blocks require special test equipment, usually run manually.

Several tools can evaluate a design to grade its testability. Some can insert test points and flip-flops to improve the chip testability and reduce the number of tests required.

Reliability. The probability of chip errors increases dramatically as the number of blocks grows. Suppose we are 95% confident that each block works. What can we expect when we put 15 blocks together on a chip? A 50% likelihood that it will fail! So the total testing cost for each block on larger chips can increase very steeply.

Frequency. A chip may be running a thousand million operations a second. If the error rate is only one in a hundred million, there could still be 10 errors a second! The problem of chip failure thus grows not only with complexity but with increased speed.

We may tolerate a failure in our personal computer or cell phone every few hours, but not in our car engine or airplane!

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