Design using Standard Description Languages

Introduction

VHDL as a hardware description language is be- coming even more popular in the field of the development of digital hardware and it offers a wide range of possibilities for dealing with ever increasing requirements. The following sections, along with several examples, give a basis for the practical interpretation and present an approach to problem solving for frequently asked questions. The sections follow on systematically, bringing together the different aspects to give an overall picture. The aim therefore is not only to present a complete syntactical language description, but to emphasize the important elements used in the prac- tical implementation of a synthesizable design.

Points of main topics:

• Structure of VHDL designs;

• Concurrent und sequential statements; applica- tion in synchronous designs;

• Structure of a simulation environment.

The Foundation of VHDL

VHDL is a description language for digital cir- cuits. It was developed by an initiative within the VHSIC programme (Very High Speed Integrated Circuits) of the American Ministry of Defence. The driving force was the difficult situation that suppliers used different description languages for the development of their systems. This made it almost impossible to exchange designs or to be able to work together on larger projects. Also there was no guarantee that the individual languages would last the lifetime of the systems.

The solution was a standard language with a guar- anteed future. At the beginning of the 80s the first versions of this language were mentioned, which gave it the name VHDL (VHSIC Hardware Description Language). Following on from that the Institute of Electrical and Electronics Engineers (IEEE) developed this as a standard language which was ratified in 1987 with the title IEEE 1076 (VHDL‘87). This opened the way for the development of the next generation of integrated circuits.

In comparison with the classical method of design at the gate level, the new method is more suitable for larger and highly complex designs. Above all, the various possibilities of the early detection of conceptional and logical error during the simulation increases the quality of the design and reduces the period of development.

VHDL is mainly a technology independent description, therefore it is possible to create designs for a chosen technology using synthesizing tools. This characteristic is a requirement which allows one to keep up with the fast development of semi- conductor technology. Not only is the aspect of the shifting of existing designs important, but also the re-use of already tested and proved compo- nents. The standardization of VHDL is also not completed. Owing to the increasing usage of this language it is necessary to make regular extensions and amendments. The last extension took place in 1993 (VHDL’93). This status is recorded in the IEEE standard ‘VHDL Language Reference Manual’ [4.3] and is also the basis for this introduction to the description language VHDL.

VHDL Design Cycle

VHDL supports all phases of circuit develop- ment.

Typical steps are:

• System modelling (specification);

• Description on the register transfer level (de- sign);

• Netlist (Implementation).

Because of its high versatility, access to the lan- guage appears to be complicated. First steps seem to be very difficult. However, VHDL is a multi- layered language. It offers distinctive features for each of the three phases mentioned above. For a practical application it is only necessary to use a subset of the entire vocabulary. This makes it easy to keep track of things, and simplifies learning.

The Phase of Specification

The system model contains algorithms regardless of the possibility of the model being able to be synthezised. Using a formal specification a first

count, and clock frequency, the circuit developer has the difficult task of mapping program language statements (IF, ELSIF, CASE, ...) in an optimal way to the register transfer level. In detail this describes the type of combinatorial logic and the way signals are passed from one flip flop (register) to the next. Figure 4.1 shows the structure of a

Design using Standard Description Languages-0050

fully synchronous design. In this phase the primary interest is focused on the way in which the circuit interacts with other parts of the design.

Register Combinatorial

model serves to investigate the system’s response and hence its functionality. This allows the orderer and customer to find out if the problem has been understood and if all requirements have been met.

The main effort focuses on algorithms which de- scribe the principle behavior of a circuit.

The Phase of Design

During the next step the formal specification is converted to a description which can be synthe- sized. To meet requirements, e.g., chip area, gate

The description can be in text or in schematics such as block diagrams, flow charts, state dia- grams, and truth tables, followed by an automatic VHDL code generation. Figure 4.2 shows a typical example.

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One of the big advantages of VHDL is the possibil- ity of designing a test environment, which is called a test bench. The test bench allows the stimulation of the inputs of the circuit under test with realistic signal patterns. Simulation shows whether the outputs produce the expected responses. Verification of the simulation results can be done by the test bench itself. Figure 4.3 shows the simulation results of a circuit model which enters all states and performs all state transitions once. Simulation and verification of results take a huge amount of time in a design cycle. It is necessary to make sure that there are no functional errors, which means that the design is ready for the next step: the synthesis.

Design using Standard Description Languages-0052

Design using Standard Description Languages-0053

At times a critical path can appear after synthesis. Sometimes it can only be removed by a change of the VHDL description. In the worst case this could imply a change of specification. As a consequence there could be several iteration loops on the way to a useable netlist (fig. 4.5).

The Phase of Implementation

Is it to be an ASIC or a FPGA? Physical realization only depends on the library attached during synthesis. Assuming the synthesis tool has access to all relevant data, the generated circuit is a true picture of its textual description made in the first design step. However, it is very difficult to understand the functionality of all the gates in detail.

Requirements regarding area and speed are met by the tool in an optimal way. A simulation of the synthesized circuit at the gate level, compared with the simulation results of the design phase, must produce identical results.

The first two phases (specification and design) can be performed in one step if it is a small and straightforward design. That means that the modelling of the system is carried out using a description which can be synthesized at the register transfer level. Synthesizing the design, normally carried out in the third phase, runs automatically. Thus describing a circuit at the register transfer level using VHDL will be the main issue and the main point of interest in this chapter.

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