Synthesis:Modification of Hierarchy

Modification of Hierarchy

It is not always possible to plan partitioning prior to the design in a way to obtain an ideal set of logical modules with a suitable hierarchy. For example, components originating from earlier de- signs do not fit properly into the actual concept, or a modification in the design changes partitioning. In such cases it can be necessary to change the hierarchy in parts or in the whole and to restructure anew. Restructuring can be done in two ways: either by changing the VHDL design, or by using suitable commands during synthesis. To perform that task the Synopsys compiler knows the commands group and ungroup, and allows an optimal partitioning to be found experimentally.

Ungroup Command

The ungroup command removes an existing level of hierarchy, e.g., when many modules having a small content obstruct optimization. The example in fig. 6.14 shows that case. After the command ungroup all cells are part of the same level of hierarchy.

Group Command

Having a flat design, new levels of hierarchy can be established by using the group command. This statement allows one to collect objects of the present level of hierarchy in a new module. The command is very versatile because objects can be single gates as well as blocks, processes, or components, immediately after reading the source code.

Synthesis-0021

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