Design using Standard Description Languages:Process
Process
As shown in the previous chapters, concurrent statements are only legal within an architecture. Concurrency is an important requirement for de- scribing digital circuits. However, complex sequences of events are difficult to describe using the language constructs known so far, such as simple, conditioned, or selective signal assignments. Each modern programming language pro- vides constructs for supporting a structured programming style. Because of that, sequential language constructs such as IF ELSIF, CASE or loops must be available in VHDL as well. So far there is no answer to how to describe a combinatorial or synchronous design with a higher complexity. Within VHDL the process is the answer to this question.
Being a part of the architecture, a process acts concurrently from an external point of view. Internally it provides space for sequential statements, hence combining the requirements for a hardware description language and the demand for structured programming ideally. These properties turn the process to the most used statement, which ex- plains its central role in VHDL. At a later point in time it will be obvious that the signal assignments mentioned above represent a simplified form of a process.
Properties
A process contains sequential statements. The program execution is defined by this sequence. The behavior of other, non-concurrent, languages and VHDL can only be compared partly. The main difference between a process and a classical pro- gram is: the process, under normal circumstances, will be repeatedly activated. An obvious example are processes used in synthesizable code.
Structure of Processes
Processes may be located anywhere in the state- ment region of an architecture. A process always contains a sensitivity list, a declarative part, and a statement part.
The process will be activated when a signal in the sensitivity list changes state. A process is either in the state ‘executed’ or ‘suspended’. An event in any of the signals in the sensitivity list causes the process to be executed. After the last statement the process is put into the suspended state and waits for a new event.
Process Declarative Part
This part is used to declare types, functions and procedures. Its main purpose is to declare signals and variables (see section 4.2). All these statements are used locally. They are only known and valid within this process. 4
Process Statement Part
The process statement region contains sequential statements executed as a consequence of an event in a signal in the sensitivity list. The following constructs are sequential statements:
• IF, CASE, LOOP, WAIT;
• Assignments of signals und variables.
The reserved words BEGIN and END define the statement part within the process and mark a part of the circuit which belongs together. This could be a counter, adder, or a state machine.
The example presents a VHDL process containing combinatorial logic only and no storage elements or registers.
For combinatorial processes the rule applies that all signals being read must be mentioned in the sensitivity list.
That process, describing an addition, can only produce a correct result in the signal sum when it is sensitive to any change of the input signals in_a and in_b. An incomplete sensitivity list causes unexpected results or models that can not be synthesized. The worst case is that the simulation prior to and past synthesis differ. Some synthesis tools ignore the sensitivity list because they as- sume a process is to be re-executed if there was a change in a relevant signal. Assuming the signal in_b is not mentioned in the sensitivity list, the VHDL simulator will only calculate a new result at a signal change of in_a. This means: if only signal in_b changes its value the signal sum will keep the present value, which is wrong by now. If the synthesis tool assumes the same, it will ‘try to keep the actual value’, inserting a storage element (latch). Normally this is not wanted. Even worse, it is not desirable at all.
As a supplement, the use of the type NATURAL – a subtype of INTEGER – is mentioned to reduce the value range to natural numbers. An additional reduction to the range 0 to 15 is caused by the statement RANGE 15 DOWNTO 0.
Signals and Variables
Signals
Signal assignments within a process act com- pletely differently from the concurrent statements the rules of inertial or transport delay (see section 4.4.3).
The example of section 4.5.1 should be changed in a way that, if it exceeds the value 10, the result would be reset to zero (fig. 4.31). At the first glance it seems that the following implementation describes that behavior. However, a more detailed analysis shows that an erroneous function can occur. That would be the case when both input signals take a value larger than 5 at any point in time (e.g., t = 20 ns). What is happening is then shown in table 4.4 in detail.
presented so far. Without knowing some details, processes hide some potential sources of error. Valid in any case is:
A process as a whole is a concurrent statement.
To be processed, it takes exactly one delta of simulation.
Signals within a process do not change their value during process execution. Signal assignments show, as long as they do not have delays, re- sults not before the end of the process. This is a simulation delta later. Signals being read in a process produce values coming from preceding cycles of simulation. This assures concurrency related to other processes. Within a process several assignments, following each other, to the same signal, are valid. However, only the last mentioned assignment stays in effect. Signals carrying a delay time will have the assigned value written to the driver list at the proper point in time, according to The workflow within a process is sequential. The first line calculates the sum and passes the result to the signal sum. The second line finds out whether the legal range of values was exceeded and resets; in the third line, if necessary; the signal sum to 0. Because the execution of signal assignments within a process is performed sequentially, an assignment performed later can overwrite a prior assignment. The execution of assignments is per- formed sequentially; however, the assignment of new values to signals is made at the end of the process or at a break caused by a wait statement. A change of state in a signal is visible not before the next simulation delta. The example above shows a comparison using values from the prior simulation delta. Hence, depending on the history, the signal sum can take values larger than 10.
Because the process is sensitive to a change of the signal sum, which has now just changed its value, it will be resumed. The following simulation delta will produce a comparison with the true condition. The statement in the third line will then be executed. Continuing this analysis shows that the result can not be stable. The value of signal sum changes between 0 and 12, every change of the signal adds another simulation delta (see section 4.4.2).
Variables, like signals, should be initialized. This is done explicitly by a declaration or, by default, it takes the left value presented by the type dec- laration, which is a ’U’ for STD_LOGIC. Initial- ization is performed only once at the start of the simulation (t = 0 ns) and not, as sometimes assumed, when a process is re-entered. Care must be taken when initializing signals, because hardware normally can not perform that operation, and, as a consequence, synthesis would ignore initial values of signals. The following example shows a correct behavior according to specification and is a typical application of a variable.
to store intermediate results on a signal. That is the reason for useing variables as an important supplement for describing sequential activities in VHDL. Variables obtain their value immediately after the assignment. The value is available within the actual simulation delta and can be used at once for further operations in the process. An assign- ment to a variable is always performed immedi- ately. This implies that it is impossible to add a time delay (AFTER ...) to a variable assignment. To emphasize that fact variable assignment has a different symbol.
When declaring a variable there is no restriction on its type. However, the range of legal values of the variable is limited to the process where it has been declared.
Shared Variables
Normally signals are responsible for process to process communication. VHDL‘93 defines a global variable by using the add-on SHARED in its declaration. This global variable can be
used by several processes and, because of that, for communication between processes. Unfortunately this feature is not supported by all synthesis tools. In this context it is not yet defined when two processes, during the very same simulation delta, try to access the same variable in a write write or write read mode of operation. The only meaningful application would be a data transfer in one direction only, such as process A writes to the variable and process B reads from the variable. A declaration of a global variable can only be carried out in the declaration part of the architecture, next to the signal declaration.
Sequential Statements
Sequential statements can be found in processes, functions, and procedures. This part describes individual constructs, shows examples of application when describing combinatorial logic, and identifies typical sources of error.
IF THEN ELSE
The IF statement forms the skeleton of a multiplex structure and can be compared with a conditioned, concurrent signal assignment (see section 4.3.2). Controlled by at least one condition, the IF statement decides which branch is to be processed That is why ELSE must exist only once in the last branch.
Nested IF constructs are legal, but if there are more than two nested IF statements it should be examined whether a different structure provides an improved overview and a better readability. Deeply nested levels produce a lot of alternatives, often mutually exclusive, with an insecurity if the choice of priorities is made correctly. In a complex system several assignments within a branch are more often the rule than the exception. Then synthesis produces separate multiplex structures for each data path (fig. 4.33).
The sequence of alternative branches defines their priority. Only statements of the first condition returning a true value will be executed. All other branches will be ignored. If no condition returns a TRUE value the ELSE branch will be executed.
If a process should produce combinatorial logic
only, care must be taken to make sure that in all existing conditions an assignment to each signal is made or a terminating ELSE branch is present. Similarly to the case of an incomplete sensitivity list a missing signal assignment causes the syn- thesis tool to insert an unwanted storage element (latch). This is because the synthesis tool assumes that, in this case, the signal values must be pre-
In the following example a typical application for the IF statement is shown.
❑ Example: Address decoder
An address decoder distributes the address space available amongst peripheral units. The process ‘decodeA’ decodes the full address space, whereas ‘processB’ only prepares the selection to a maxi- mum of 16 pages of 4k each. To address a piece of peripheral equipment, the corresponding chip
CASE WHEN
Similarly to an IF statement, CASE statements allow a branch of program flow depending on a signal’s or variable’s value or on the result of a logical expression.
To control the program flow only a discrete data type (such as INTEGER or ENUMERATOR) is allowed. However, this offers a wide range of possibilities, because most of the signal types are declared to be of the type ENUMERATOR. The CASE statement can be compared with a table. ‘expression’ indicates the line in which the instruc- tion to be executed can be found.
After synthesis has been carried out, once again, we will find multiplexers in the hardware. Branch- ing alternatives always depend on only one input. They are mutually exclusive. Because of that, at times the CASE statement is the better choice, because multiple branches in IF statements assume independent controlling conditions.
The loop allows the repetition of a part of a VHDL program several times, for example to process each element of an array in the same way. If the pro- gram is to be synthesized it is important to know how often the loop will be processed, because this determines the complexity of the circuit. In a FOR
subsequently takes all values as defined in the type declaration of states;
• The use of a signal ‘parity’ instead of the vari- able is not possible, because the result would be the very last assignment to the signal with the parity calculated in the preceding simulation delta. parity <= parity XOR data_in(0).
Use of the EXIT command
❑ Example: Counting leading ’1’s in a WHILE loop
A WHILE loop is a big challenge for a synthesis tool. A WHILE loop can not be synthesized if the compiler can not detect the maximum number of iterations or if the maximum number is a condition dynamically evaluated at run time.
In the following example a WHILE loop is used to count the number of leading ones in a data word. The first zero being detected causes a break of the loop. Assuming the vector only contains ones, the loop is terminated with the EXIT command because the index of the vector ‘data’ must not exceed the value 15 (run time error). The result cnt serves as an index to address individual bits of the vector at the same time.
The sample VHDL code can not be synthesized, because the index cnt is changed within the loop. It would be better to realize that task using a FOR loop (process countB).
So far the sensitivity list of a process exclusively decides when the process is to be executed. An alternative path of a process employs a wait in- struction, instead of the sensitivity list, to put the process into a suspended state. For synthesis, how- ever, there are substantial limitations when using the wait statement. There must be only one wait statement, either at the beginning or at the end of the process. For the simulation only, this statement offers quite a lot of possibilities to handle process flow.
Processes which have a sensitivity list are executed once, during the so called elaboration phase for initialization, at the start of the simulation. The WAIT statement at the end of the process is an equally good replacement, because all statements placed in front of it are at least executed once at the start of the simulation. The initialization of a process in VHDL has no counterpart in hardware. That is why initialization can be switched off in some simulators. This prevents the simulation starting in a well defined state, whereas the synthesized circuit could enter an undefined state. That is the reason for placing the wait statement at the beginning of a process.
The assert statement is a suitable tool for trapping an erroneous behavior of the VHDL model. The statement knows, based on a boolean expression, the correct situation and announces every discrepancy during simulation. The assert statement is, depending on its location within VHDL code, con- current when placed outside a process, or sequential when placed inside a process. Its form remains the same, but the sensitivity list will be different. The concurrent statement is sensitive to all signal changes of the logical expression, whereas the sequential statement is tied to the sensitivity list of the associated process.
If the logical expression returns the result FALSE a message is issued. Without a REPORT statement the message simply is ‘assertion violation’ plus stating the module, which causes the error. The level of the error status decides if the simulation is to be continued.
NOTE: This error status denotes insignificant out- put, such as general comments regarding the state or progress of the simulation or a notification of time consuming computing activities. WARNING: A warning indicates a situation which is exceptional but not necessarily a fault.
The simulation can continue.
ERROR: Replacement value when no error states are specified. In this case often a condition is not met, which causes things to go wrong. Often simulation will be terminated.
FAILURE: A severe error condition occurred, e.g., division by zero. Simulation will be terminated.
NULL
Sometimes it is useful to have a statement which does nothing at all. The NULL statement could,
e.g., be situated in a branch of an IF or CASE statement. VHDL requires the explicit use of a NULL statement, the opposite of the programming language C in which an additional semicolon pro- duces an empty instruction.
At the end of this chapter an example of a typical application will be presented. Some of the compo- nents discussed so far will be used.
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