Design using Standard Description Languages:Sequential clock synchronous logic
Sequential clock synchronous logic
Digital systems such as processes, finite state ma- chines, or communication equipment need a clock. The clock determines their operating speed and is responsible for partial results being present at the right point in time. Without a clock pulse the circuit remains in its actual state. In CMOS technologies this halt of activity causes a small, often insignificant, quiescent current. If the circuit consists of several parts or if a result depends on the present state of the circuit, a clock ensures a regular and well defined flow of events. The whole circuit only changes state when a special event occurs, for example a rising edge of the clock. Consequently the storage elements (registers or flip flops) change their values at the same time, synchronously with the clock. The principle can be compared to a bucket chain, working only when all participants take the bucket coming from one side and pass it over to the other side.
The design of a clock synchronous circuit is called a ‘description at the register transfer level’, having transfer functions to describe the data flow be- tween registers. In hardware, flip flops often make up the registers, whereas combinatorial operations implement the transfer function (fig. 4.39).
Partitioning a design into individual registers and transfer functions is an important step in the design cycle of a digital circuit. The synthesis tools expect that structure in a VHDL description too. This chapter shows how to describe synchronous state machines using VHDL and points out when to take care if a synthesis is to follow.
Combinatorial Logic
VHDL offers a lot of possibilities for describing combinatorial logic. Some of them have already been covered in the chapters before. This includes:
• concurrent statements and the use of the logi- cal operators such as AND, NAND, OR, NOR, XOR, XNOR and NOT;
• Conditional signal assignment using WHEN ELSE;
• Selected assignments using WITH SELECT;
• Arithmetic operations, sequential or concurrent
All expressions mentioned have in common that they can be realized in hardware by a combination of basic boolean functions such as AND, OR or NOT.
edge (set up time tS) and after the active clock pulse (hold time tH).
The sampled value will not appear at the output immediately, but, owing to an internal propagation delay, some time later (clock to output time tCO) (fig. 4.41).
Registers and D flip flops
A register has the task of storing intermediate re- sults and keeping a signal’s value during a clock period. The edge triggered D flip flop does that job by passing the value at input D to the output Q when a rising or falling clock edge occurs (fig. 4.40). This process is called ‘sampling a signal’. Looking at flip flops existing in the real world, there are two conditions to be met to make sure that the output takes the right value.
The signal on an input of a flip flop must be stable between a specified time prior to the active clock The signal assignment D to Q has to occur at every rising clock edge. Hence the process must be sensitive to the signal clock. This causes an execution of the process at every signal change. Activating the process execution at positive clock edges can only be done by the statement: IF(clock’EVENT AND clock = ’1’). The attribute ’EVENT (to be
The example describes an ideal behavior. There are no propagation delays, therefore the assign ment will be valid already within the next simula tion delta. Besides, set up and hold times must not be checked during simulation, as a synthesizable YHDL code does not contain timing information. A precise timing analysis will be performed after synthesis (fig. 4.46).
Clocked Processes
As it would be tedious to describe every register or flip ftop on its own , the synthesis tool recognizes whether storage elements are to be inserted. A clocked process describes the combinatorial part of the circuit as well as registers used for sampling or sychronization.
Clocked processes have the following characteristics:
• The process is sensitive to a clock;
• The process starts with IF (clock' EVENT AND clock = ' 1')
Without a change to the circuit both processes P I and P2 can be combined to obtain smaller modules belonging together.
The sequential statements of section 4.5 are impor tant for describing the behavior of the simulation. Assignments in clocked processes are made with each active (e.g., rising) clock edge. The signals themselve s do not change during the execution of the process. The new signal value, after an active clock edge, is a result of a boolean combination of signal values prior to the edge. This corresponds to the circuit structure of fig. 4.42 and coincides with the behavior of real circuits.
Reset in Clocked Processes
Registers are storage elements and take a random value after the supply voltage has been applied. The correct operation of the circuit often depends on a defined starting value at the output of the register. Initialization of registers is performed with a special signal (reset) which is connected to all registers. This (hardware) initialization must not be confused with initialization in a signal dec-
laration! A signal explicitly designated as reset can often not be avoided in a VHDL simulation, because at the simulation’s start signals of the type std_logic take the value U (undefined). Structures with a feedback do not have a chance of going past the undefined state, because a boolean combination of undefined U and 0 or 1 results in U again. However, in the real world, after power up, a circuit must not enter a state which needs a reset.
There are two ways in which to realize a reset, the synchronous or the asynchronous way. Having a reset working asynchronously, the register will be reset independently of the clock signal. The reset signal has a priority in this case. On the other hand, a synchronous reset is realized by a boolean operation in the data path (fig. 4.47).
Clocked Process with an Enable Function
In many cases it is desirable to stop activities in clocked processes during one or several clock periods, or to make signal assignments only when a valid input signal is present. A dedicated signal (enable) takes control and makes sure that the register retains its actual value if there is an in- terruption. This is carried out by a feedback from the output to the input (figures 4.48 and 4.49).
Fig. 4.49 Principle of clocked processes with an enable function: processed only when enable = ’1’
Variables in Clocked Processes
As shown before, variables take their values immediately after an assignment. That is why they have a special status in a clocked process. The answer to the question of whether a register for a variable is to be synthesized or not depends on the location of the variable within the process. Assuming the assignment of the variable occurs prior to its evaluation, no register will be synthesized to store its value. In that case the variable is a substitute for a complex expression. On the other hand, if the variable were be read prior to its assignment, a register will be synthesized to memorize the value from the preceding clock cycle.
Processing of Asynchronous Bus Signals
In clock synchronous circuits, input signals with no reference to the clock signal must be looked at more closely. If it is a single signal (e.g., STD_LOGIC) the asynchronous signal can be ‘synchronized’ using two or three cascaded flip flops. A change of state on the asynchronous signal will be detected with a resolution of a clock period. This principle can not be applied when asynchronous bus signals (e.g., STD_LOGIC_VECTOR or INTEGER) are concerned as each signal of the bus can carry a displacement of one clock period.
❑ Example: the transfer of a bus signal (count) between two systems having two different operation clocks (clock1 and clock2) will be examined.
It is not the bus (named count in the example) that is going to be synchronized, but two control signals (request and acknowledge) which request and acknowledge a transfer. Inverting the signal re- quest initiates the transfer, inverting acknowledge indicates the value to be transferred is available in an intermediate register.
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