Synthesis:Partitioning

Partitioning

An important condition for a good result in the synthesis is a careful partitioning of the design. This means dividing the whole circuit into modules, which could show at the same time a hierarchy, or, in other words, a nesting of modules. The earlier partitioning is taken into account in the design cycle, the simpler synthesis will be. A change of the module boundaries often causes a re-definition of the interfaces which is time consuming and a source of error. So far there are no explicit rules for performing partitioning, but the following recommendations help the right decision to be made.

Combinatorial parts connected with each other should be in the same module (fig. 6.9).

The example in fig. 6.9 contains three combinatorial parts which are; directly or indirectly; elements of the critical path (the signal path which has the maximum delay time). In this case, when optimizing the synthesizing compiler has more degrees of freedom to take the edge off a critical path by  choosing an advantageous combination when combining logic. A starting point which is not as good can be seen in fig. 6.10. There the compiler can not combine or relocate logic across the hierarchical levels.

Synthesis-0017_thumb

Still looking at the partitioning in fig. 6.10, another difficulty is the distribution of the delay amongst the individual combinatorial parts. Because of this the driver strength and the loads have to be taken into account. To optimize each individual module, precise specification of the maximum delay time (output- or input-delay), the expected load, and driving strength must be made at the interface q (fig. 6.11). Figure 6.11 uses some statements of the Synopsys compiler to do that.

Synthesis-0018_thumb

Registers at all outputs

Registers at all outputs of the modules reduce the number of constraints and simplify synthesis as a result. Which input load is to be taken into account at a module input can easily be decided using this recommendation, because as a rule it is the driving strength of a flip flop. The input delay of a module related to the clock depends only on the propagation delay of the register (clock to output, tco) of the preceding module and not to a lot of unknown and variable amount of combinatorial operations (fig. 6.13). Hence the critical path is only within the module. The optimization in time can be done more easily; for example by a new optimization run using changed, new constraints.

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more