Synthesis

Introduction

Hardware description languages support the development cycle at a higher, more abstract level, as it was the case at the gate level. The interface to the silicon foundry or programmable logic is still a netlist at the gate level. Logic synthesis combines both levels, automatically compiling the source code from the high level language to an optimized circuit at the gate level. This process has two phases:

• Compilation: The RTL description is translated to a generic, which means a technology-independent netlist not yet optimized in this stage.

• Optimization: Mapping of the generic netlist to a target technology. The result must satisfy requirements in area and operating speed.

Not only is an efficient optimization algorithm a prerequisite for a successful synthesis, there must be an agreement on what type of hardware will be generated by special high level language constructs; last but not least, reproducible results must be ensured. Each synthesis tool uses a so called style guide, which is a collection of VHDL examples, as a reference. This manual does not explain in the first place which structure at the gate level is produced by an IF or CASE statement. Instead, it is a guide to telling what a process description should look like to describe a combinatorial circuit embedded within registers, or which statements of the high level language result in a pin which has tristate properties; just to name two examples. The VHDL code fragments in fig. 6.1 also show the dependence on the result of the synthesis and the quality of the source code. Whereas the first suggestion compiles to an adder, subtracter, and a multiplexer, the second version only needs an adder and a multiplexer at input b. These structural differences can hardly be adjusted by the optimization tool

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Section 6.2 shows a part of the guidelines for structuring code of the companies Altera and Synopsys. Some recommendations to support synthesis by a good partitioning of the design follow in section 6.3. The next chapters deal with optimization, explaining basic algorithms and strategies. Lastly, there is a table listing VHDL constructs which can be synthesized.

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