Design using Standard Description Languages:Advanced VHDL.

Advanced VHDL

Generics

The re-use of already developed, simulated, and working circuits is a more frequently requested primary goal. ASICs and FPGAs are capable of integrating highly complex systems on a small piece of silicon. But only by re-using available components, the capabilities of logic cells are fully utilized. Unfortunately the attempt to re-use com- ponents can go wrong, because of different operating conditions or an architecture which depends heavily on a technology available at an earlier point in time.

Generics help to parameterize a circuit. Generics are a special kind of constants for modifying the properties of components. E.g., when designing an 8 bit architecture, a future employment in a 16- bit environment can be taken into account. One can think of combining several components with similar functions into one design, and define special properties of the individual component at the time of instantiation by using suitable generics.

Generics are declared in the entity declaration prior to the port list. Hence generics are accessible in the interface description as well as in the associated architecture.

To explain the use of generics, the parity generator in section 4.5.3 will be modified in such a way that it can be used with signals having any bus width.

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