Summary of Back-end Design Tools (Physical Design)

Summary

We discussed all the IC BE design steps and tools. We have gone from design methodologies all the way to first silicon.

Physical layout includes floorplanning, placement, and routing. Floorplanning arranges the major blocks on the chip. Placement arranges the smaller blocks or cells inside the blocks.

Routing traces out the wiring paths. There are several routing styles. Global routing connects major blocks, and detail routing handles the wiring inside blocks down to the transistor level. Channel routers are used for standard cell blocks.

BE design has many checking tools. Electrical rule check (ERC) checks electrical rules for gate interconnection. Design rule check (DRC) checks physical spacing and sizing rules for layout and placement. Logic versus schematic (LVS) checks that the physical wiring matches the schematic or HDL description.

After the place and routing, extraction tools compute the physical lengths of wires and spaces. Delay calculators use this information to predict accurate gate and wire delays. A static timing analyzer tool analyzes signal delays through gates and wires to ensure that no signal or clock is late. Clock pulses control the flow of data through the logic. Timing closure is the process of fixing all the timing violations without causing new ones.

Signal integrity tools analyze noise and interference from other signals in the chip. Low-voltage chips are more sensitive to noise. An even power voltage all over the chip is required, as the circuits operate over a small voltage range. Voltage sensitivity tools analyze the design to ensure that all points on the chip remain within the range.

Small chips with fast switching can consume a lot of power and run hot. Thermal design tools check for hot spots.

Several manufacturing steps lead to first silicon. Product engineering and diagnostic EDA tools analyze the first chips to ensure that one or more work.

Process porting tools help move an existing design to a new process.

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