Design using Standard Description Languages:Packages and Libraries

Packages and Libraries

VHDL supports the encapsulation of data, components, procedures, and functions in a so called package. A package combines multiple used declarations and distributes them amongst several de- sign units. Compared to a library, which is responsible for the re-use of complete designs, a package preferably contains the tools to manage the re-use. It can be compared with ‘include files’ of other program languages.

The Structure of Packages

A package has two parts:

• A package declaration;

• A package body.

The package declaration defines an interface to a package. Similarly to a table of contents, it lists what is available in the package. It deals with the visible aspects of the package and offers, using a type or function declaration (prototypes), a kind of operational manual for the user.

The package body contains the implementations of functions and procedures. The user only wants to know if the requested function is present and what type of input and output parameters are required. This part is optional, it can be omitted if there are only type or constant definitions in the package.

To access the contents of a package a USE statement must identify the library, and within the library the parts of the package to be made vis- ible for the actual design. The most frequently used statement is the employment of packages STD_LOGIC_1164 from the IEEE library which offers the type STD_LOGIC.

Design using Standard Description Languages-0184

Libraries

As a rule, a complex VHDL design is distributed to many different text files. Each file contains one or more design units. There are five classes of design units:

• Entity declaration;

• Architecture;

• Configuration declaration;

• Package declaration;

• Package body.

In the first phase the VHDL compiler checks the syntax and semantics of each design unit prior to the compilation phase, which transforms the VHDL text into a form only a computer can read. Often the work flow of a VHDL text, that is, the separation of design units and the compiling to C++, leads to a linkable assembler code. When the simulation starts, the choice of a configuration or of an entity architecture pair decides what is to be simulated. Based on these instructions the simulator can choose the corresponding object files and link them to be simulated.

All files necessary for running a simulation form a library. Its file structure and management is a responsibility of the simulator or the computer sys- tem, they are not specified by the VHDL standard. The VHDL standard only covers attaching libraries and accessing design units contained there. A logi- cal name will be assigned to the library. This name will be used in VHDL. Linking the logical name and the physical storage area is a job of the simula- tor. The library with the logical name WORK has a special meaning. This library represents the actual working library and defines where the compiled VHDL texts are going to be stored. So before the compiler can start, the symbolic name WORK must point to an existing library (fig. 4.66).

tors, can be found in the library IEEE as package STD_LOGIC_1164. This library, however, is not a part of the language itself.

Overloaded Operator in a Package

❑ Example: Implementation of a function for adding two STD_LOGIC_VECTOR operands Because this function is needed several times, it is part of a package.

The overloaded ‘+’ operator is only seen from outside. The function vector_to_int is only locally available within the package body. The function presents an intermediate result, normally of no interest.

Design using Standard Description Languages-0186

Design using Standard Description Languages-0185

There is a pre-defined library STD. It contains the packages STANDARD and TEXTIO (Ap- pendices C.1, C.2). Apart from that, the nine- valued logic system of the IEEE standard is widely spread. Its definition, providing overloaded opera-

Comments

Post a Comment

Popular posts from this blog

Design using Standard Description Languages:The simulation model in VHDL

Image
The simulation model in VHDL After a look at concurrent signal statements in chapter 4.3, basic mechanisms of the language can be discussed in detail. Originally the language VHDL was developed for simulation only. A dis- cussion about the theory of operation of a VHDL simulator helps to understand VHDL modelling and simplifies the choice of suitable language constructs to describe hardware constructs. The topic simulation model has an emphasis on: • Driving signals; • Delta delay mechanisms; • Modelling of delay times. Drivers Every concurrent statement, including processes, causes an event responsible for the progress of a signal. Within the simulator there is a list containing points in time to schedule signal events. Such an entry in that list is called a transaction. This list is the basic information for scheduling signal values during simulation (fig. 4.22). A change of a signal value caused by an entry in that list, is called an event in that signal. If a new entry is the ...
Read more

EDA Tutorial:Place and Route in a Standard Cell Design Style

Image
Place and Route in a Standard Cell Design Style In the design of FPGA circuits, after the synthesis of the EDIF files, the compiling and programming of the FPGA device, everything is defined and the component is completely configured. With ASIC designs, there are two possible scenarios: • Delivery of the design to an ASIC provider in the form of a so called simulate d netlist (EDIF); • Place and Route of the design with one’s own tools, verification of the results, and delivering of the design as a geometrically exact GD S II File . For similar designs in industry the netlist version is frequently chosen, but here the second scenario which includes the bac k en d processing , the phys- ical design, will be demonstrated in more detail. This needs special software tools, which allow the mask design at the lowest geometry level, and tools for checking the generated geometries against the predefined design rules ( Desig n Rule Che c k , DRC ), and allow one to extract parasitics and el...
Read more

Overview of EDA Tools and Design Concepts:Major Classes of EDA Tools.

Image
Introduction In the next few chapters, we will discuss specific kinds of EDA tools. In this chapter, we provide an overview of the EDA tool world. There are several EDA-related concepts which are helpful to understand the EDA tools and the design process. These include: Design Views Hierarchy Design Chip Architecture Methodology Design Flow Tool Suites Nora of Sandbox, Inc., is meeting again with Andrea, an ASIC engineer who works for Fabless Design, Inc. Nora has asked to learn more about the use of EDA tools. Let us listen in on their discussion. Nora: Hello again, Andrea. Did you like the party the other evening? Andrea: Yes, very much. Sandbox has both outstanding tools and great parties. Nora: We seem to be continually developing new tools. I am a little unclear why that is. Tool Improvements Andrea: That's because each generation of semiconductor process improvements shrinks the size of the transistors and wires. The number of transistors and wires...
Read more