Front-end Design Tools:Verification Tools

Verification Tools

Nora:

After the design description is entered and de-linted, then what?

Luigi:

Once a design description is "clean," we need to verify its functions (does it work as expected?). The designer prepares a sequence of inputs to the logic (block or chip) with expected outputs.

The inputs consist of a set of signals going into the logic. A set of output signals comes out of the logic. The digital signals are two level (high or low) electrical voltages. You recall that the two voltages can be called ones and zeros as well.

These input and output data sets are known as test patterns or test vectors. They are prepared manually, or with the help of an EDA test bench tool. A test bench is a software platform that helps to create test patterns and to run the tests.

We can talk later about other EDA tools which automatically generate additional vectors for manufacturing test.

Design Verification

Nora:

Why is it so hard to verify the design?

Luigi:

Errors occur in the requirements specification, the engineer's design ideas, the design capture, and in the tests themselves. That's why the verification consumes so much of the development time.

Nora:

I think someone told me that it takes 60-70% of the design effort.

Luigi:

That's probably about right. As complexity increases, the verification time also increases. Let me give you a quick overview first. Modeling tools allow the designer to model key functions at a high level of abstraction. Design decisions such as choosing to do a function in hardware or software are usually modeled and evaluated at the electronic system design level.

Simulation tools verify design behavior (e.g., what it does) or performance (e.g., how fast it runs). Software simulation is used widely to try things that would be too expensive or dangerous to do directly. Aircraft simulators can train pilots without risking an actual aircraft. Power simulation is important for battery life estimates on laptops or cell phones.

Formal Verification tools rely on notes (assertions) which the designer adds into the design or as a separate file. These notes describe the intent of what the logic should do (properties). The tools check that the design is consistent with these properties.

Some tools use formal mathematical approaches to prove that a design is self-consistent or logically correct (like a grammar checker). Others check that the logic remains equivalent before and after a transformation from one level of abstraction to another. (However, just because the design is consistent doesn't guarantee it will work as expected.)

Analysis and checking tools perform all sorts of detailed error and rule checking on the design, including function, logic, circuit, timing, and power usage.

Other checks include preventing problems with layout, thermal design, power distribution and manufacturing constraints. Some checks are done at the front end, some at the back end, and some at both.

Nora:

So, there's a whole lot of checking going on. Can you explain a little more about EDA simulation?

Simulation

Luigi:

Sure. The simulation is the actual running of the tests I mentioned earlier. The design input to a simulator program is the HDL description (Verilog or VHDL). So we talk about "running the Verilog simulator."

An EDA simulator stores the design netlist and then applies a set of input test patterns to the logic. The designer (or test generator program) creates test patterns and expected outputs.

The simulator traces through the logic, finding the logic values (ones and zeros) of each gate in turn. The simulator follows all the logic paths to the outputs and compares those to the expected outputs (listed with the input test patterns). This uncovers functional, logic, and connection errors.

Nora:

So the simulators are driven by the test vectors and check whether the design works correctly?

Luigi:

That's right. In addition, they can also check for timing errors. Simulators use gate, register, clock, and interconnect delay models to calculate timing through the logic block. There are several kinds of simulation.

In event-based simulation, the simulator keeps track of the switching of each gate (an event). Clock-based simulation keeps track of changes only at clock times.

For a computer design, cycle-based simulation updates values at each computer instruction cycle. It is cycle-accurate if the timing is also correct within the instruction cycle.

Luigi:

Let me summarize verification with a quick sketch. (See Figure 6.4.)

Luigi:

Note the iteration loop: design, test, compare, fix design, or fix test, and repeat. Also note the clock—both the design timing and the speed of the simulation (run time—how long the simulation takes) are important.

Simulation Speed

Nora:

I understand simulation can take a long time.

Luigi:

Yes, the simulators can take many, many hours to run large designs. Any time we find and fix a problem, the simulation must usually be completely re-run. Various approaches have been made to speed up simulation. A few vendors make special computers optimized to accelerate the running of simulation programs. Some simulation accelerators can run simulation a thousand times faster than software alone.

Nora:

Sam, the system engineer, told me about the hardware emulators.

Luigi:

Yes, and other companies use multiprocessors working in parallel to speed simulation. Other approaches use a roomful of loosely coupled standard processors to speed up simulation.

Nora:

Those must be the "server farms" that Hugo, the design manager, mentioned.

Formal Verification Tools

Nora:

Okay, you can speed it up, but how do you know you have got a thorough test?

Luigi:

That's an excellent point. For simple control logic designs, we can predict all possible (exhaustive) tests. For complex designs such as computers, however, we cannot predict all possible sequences of instructions.

A formal analysis tool can check that the logic meets much of the designer intent. But it still cannot guarantee that the design will actually work. In practice, we usually need several kinds of verification.

Remember we have a general netlist before synthesis and one with specific parts after synthesis. The synthesis program might change the logic. Equivalence-checking tools evaluate the netlists before and after synthesis to ensure that they are logically the same. This is another kind of formal verification.

Device and Circuit Simulators

Nora:

Are there other kinds of simulators?

Luigi:

Yes. There is a whole other class of simulators for semiconductor devices and transistor circuits. Device models and device simulators predict the electrical operation of the semiconductor devices from the underlying semiconductor physics.

Circuit simulation programs predict the electrical circuit operation using mathematical models for all the components and wires.

Did You Know?

One of the oldest circuit simulators is SPICE (Simulation Program for Integrated Circuits Emphasis—University of California at Berkeley, 1975). Many variations exist, but it is still an industry standard for predicting the operation and time delays in a circuit.