The Concept of Electronic Design Automation:Top Down or Bottom Up?

Top Down or Bottom Up?

We shall now corroborate a deeper understanding of how the vast amount of geometric pattern for a chip can be created. Before starting a chip design we have to understand what the chip is supposed to do. As discussed before, the ultimate goal of the design process is to arrive at with a set of polygons ready to print on masks and submit to manufacturing. The development sequence outlined in section 2.2 is based on recursive refinement. We start at a coarse, very abstracted representation, and systematically bring in more details. Such a methodology is referred to as a top down process. When proceeding along the behavioral axis in the Y chart, top down is the only meaningful direction. There may be only one exception: during an implementation step we might discover that there is no solution, e.g. it is impossible to meet the performance requirements. Let us give a practical example: after selecting a ripple carry architecture for an adder we work out that we cannot meet the target clock frequency because the carry delay would be too long. We would then have to go back to logic level and change the architecture to carry look ahead.

Now let us consider the structural axis in the Y chart. Going down (which means towards the center of the Y) the chip is being partitioned into its components. Partitioning is a divide and conquer approach unfolding a more complex en- tity into several smaller entities. No details are known yet about the components, they remain black boxes and their content will be defined at the next level. Speaking more practically, when draw- ing the schematic of some higher level entity we introduce symbols of the next level entities and we connect them together. In the next step we would design their schematics. Recursive application of that procedure will finally bring us down to a level where only transistors, gates, or other known elements are placed. Structural design would then have been completed.

Going bottom up along the structural axis may also be meaningful: we would first design lower level modules by placing and connecting together transistors or gates, and then use the newly designed modules to build higher level modules until we are able to draw the schematic of the top level of the ASIC. This approach avoids the need to work with black boxes. If functional representations exist for all levels then it is possible to follow that approach. Analog chips are commonly designed that way.

The Concept of Electronic Design Automation-0007

In the next section we will see that the introduction of EDA removes the need for manual design work in the structural and geometrical domains. Design work is now moved into the functional domain, and, as mentioned above, top down is more appro- priate here. Modern design flows work primarily top down, as demonstrated in Figure 2.6. The left hand side shows the implementation steps that cap- ture their result in a certain design exchange format for transfer to other EDA tools. The result of the implementation will be verified before hand over to the next implementation step. The method for verification is shown at the right hand side. Usually several iterations (this includes going backwards) will be needed between RTL (VHDL) capture and synthesis, because at RTL we cannot reasonably forecast the signal delays, as they strongly depend on the choice of cell library and semiconductor technology. Quite frequently synthesis cannot meet the performance requirements, and then RTL architecture must be revised, e.g. by introducing a pipelining concept.

At the lower levels delay predictions are more accurate, and fewer iterations are required, as indicated by smaller circles. This is very fortunate because the amount of data and computational work grow when going down to the lower levels.

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