Electronic Design Automation (EDA)

The SDF Format Objective of the SDF Format SDF is an abbreviation for Standard Delay Format published by the non-commercial interest group, Accellera, a unification of Open Verilog International and VHDL International [8.4]. SDF is no language and no program but it describes how delay data should be formatted in a design process. The goal is to make that kind of data independent from the CAD programs of different suppliers. The present version is 3.0. The format is kept relatively stable and only improvements are added so that data sets from older versions are still compatible. For that reason and because version 2.1 is widely used, the following descriptions deal mainly with this version 2.1. There are SDF formats for single devices (ASICs, such as FPGAs, gate arrays, and cell based standard products) and also for multiple system modules, as shown in fig. 8.1. The SDF format must be independent of programs and still represent data of different types: • Delay Times which could be ...

EDIF (Electronic Design Interchange Format) With the onset of CAD (Computer Aided Design) methods at the beginning of the 1980s, the necessity arose to exchange design data between the programs of different suppliers. Based on an initial cooperation of interested companies, the EDIF Steering Committee was founded in 1983. The members were Daisy Systems, Mentor Graphics, Motorola, National Semiconductors, Tektronix, Texas Instruments, and the University of California at Berkley. The idea was neither to create a new language nor a new database, but rather a set of formats enabling the transport of a design from one tool to another. In other words, the goal was a certain independence from CAD suppliers. Based on those activities a first specification was published in 1985, EDIF 1 0 0. At the beginning all of the following design areas were supposed to be covered: • Netlist; • Mask layout; • Symbolic Layout; • Logic models; • Test; • Gate array; • Parametric description; • Algori...

Netlist Formats Netlists describe circuits in a textual list format. They are normally of structural type and have two main targets: • Enumeration of all devices (or parts) including the input and output pins; • Enumeration of all connections between the de vice pins. Devices are uniquely identified by their part name and their instance name. Multiple devices with the same part name are distinguishable through their instance name (see chapter 3). Node names are either entered by the user or are generated automat- ically with running numbers by the schematic editor or the synthesis program. The path gets added to the part names and node names in hierarchical design structures. A signal describes the electrical information on a node; in the following descriptions both expressions, signal and node, are used synonymously. In principle, there are two different basic types of netlists: device oriented and node oriented netlists. D e vic e Oriented Netlists In such a netlist a single ...

System on Chip Designs (SOC) In systems on a chip (SOC) one expects today not only a processor core and dedicated application- specific electronics, but increasingly also sensors, similar circuits, and possibly even micro- mechanical components. The chip may contain not only the functionality of the printed circuit board but an entire system. Examples are contactless RF ID tags, sensors with integrated evaluation electronics and several smart card applications. A high degree of integration together with simultaneous mass production leads to low prices, and the impact on the consumer market is accordingly large. There are many new products on the horizon, the market for ID tags alone is gigantic and already in start up. Concept and Specification of SOC The design of a SOC puts highest demands on the designer, not least because he has now to under- stand more technical disciplines than ever before and combine them in one model consistently. The specification of the analog blocks is one o...

EDA Systems for Hardware/Software Co-Design The design of systems with IP cores, in particular with processor cores, requires a new dimension of performance from the used software tools: • support in design space exploration after allocation of hardware and software; • Support for simultaneous, concurrent develop men t of hardware and software; • Support for verification with different models on different abstraction levels . Design Space Exploration Tools The automatic partitioning of a given task in a software and a hardware part, controlled by a forma l executable specification [7.9] is a fastidious task and still the subject of intensive research [7.4], [7.7]. These efforts are concentrated on complex applications of signal processors (ASIP) where algorithms are well defined by a C language model or in a special specification language like Spec C [7.9], [7.36], [7.37] or SpecCharts [7.39]. The mapping from such a functional description in a specification language to a given archi...

Design with Virtual Components and Processor Cores Design to Target Technology FPGA When looking at FPGA as a target technology a special situation exists: companies like ALTERA or XILINX are primary interested in selling chips. For this reason they do not offer design house activities. Their interest is to spread IP technology, so they provide and distribute cores at low cost. Libraries offered under these circumstances, and Besides standard libraries, which contain logic se- ries and well known building blocks (e.g., counters, registers, adders, etc.), more complex LPM modules are available by using the provided gen- erators. Structural block diagram set-up with in co-operation with these components is easy and effective. In the case of a language driven design, where the target functions are described within the design language, operators are effectively replaced during synthesis by firm macros. The library from ALTERA [7.1] or a similar one from a competitor, offers a large select...